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3rd semester files

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Adog64 2024-02-22 14:26:13 -05:00
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3rd-Semester-Fall-2022/Aidan Sharpe Resume 10-05-2022 (Repaired).docx Executable file
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3rd-Semester-Fall-2022/Aidan Sharpe Resume 10-05-2022.docx Executable file
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3rd-Semester-Fall-2022/Aidan Sharpe Resume 11-21-2022.docx Executable file
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3rd-Semester-Fall-2022/Aidan Sharpe Resume.pdf Executable file
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3rd-Semester-Fall-2022/Bottle Rocket Lab Report.docx Executable file
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3rd-Semester-Fall-2022/CRNs.txt Executable file
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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/Lab1.qpf Executable file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 17:41:27 September 08, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.1"
DATE = "17:41:27 September 08, 2022"
# Revisions
PROJECT_REVISION = "Lab1"

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/Lab1.qsf Executable file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 17:41:27 September 08, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Lab1_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C6GES
set_global_assignment -name TOP_LEVEL_ENTITY Lab1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:41:27 SEPTEMBER 08, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name BOARD "MAX 10 DE10 - Lite"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name VERILOG_FILE Lab1.v
set_global_assignment -name VERILOG_FILE Lab1_testbenc.v
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH Lab1_testbench -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME Lab1_testbench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id Lab1_testbench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Lab1_testbench -section_id Lab1_testbench
set_global_assignment -name EDA_TEST_BENCH_FILE Lab1_testbench.v -section_id Lab1_testbench
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/Lab1.qws Executable file
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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/Lab1.v Executable file
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module Lab1(HEX0, SW);
input [7:0] SW;
output [7:0] HEX0;
assign HEX0 = SW;
endmodule

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/Lab1.v.bak Executable file
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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/Lab1_nativelink_simulation.rpt Executable file
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Info: Start Nativelink Simulation process
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
========= EDA Simulation Settings =====================
Sim Mode : RTL
Family : max10
Quartus root : /home/sharpe/intelFPGA_lite/18.1/quartus/linux64/
Quartus sim root : /home/sharpe/intelFPGA_lite/18.1/quartus/eda/sim_lib
Simulation Tool : modelsim-altera
Simulation Language : verilog
Simulation Mode : GUI
Sim Output File :
Sim SDF file :
Sim dir : simulation/modelsim
=======================================================
Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script /home/sharpe/intelFPGA_lite/18.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
Error: Can't launch ModelSim-Altera Simulation software -- make sure the software is properly installed and the environment variable LM_LICENSE_FILE or MGLS_LICENSE_FILE points to the correct license file.
Error: NativeLink simulation flow was NOT successful
================The following additional information is provided to help identify the cause of error while running nativelink scripts=================
Nativelink TCL script failed with errorCode: issued_nl_message
Nativelink TCL script failed with errorInfo: Can't launch ModelSim-Altera Simulation software -- make sure the software is properly installed and the environment variable LM_LICENSE_FILE or MGLS_LICENSE_FILE points to the correct license file.
while executing
"error "$emsg" "" "issued_nl_message""
invoked from within
"if [ catch {exec $vsim_cmd -version} version_str] {
set emsg "Can't launch $tool Simulation software -- make sure the software is properly installed..."
(procedure "launch_sim" line 88)
invoked from within
"launch_sim launch_args_hash"
("eval" body line 1)
invoked from within
"eval launch_sim launch_args_hash"
invoked from within
"if [ info exists ::errorCode ] {
set savedCode $::errorCode
set savedInfo $::errorInfo
error $result $..."
invoked from within
"if [catch {eval launch_sim launch_args_hash} result ] {
set status 1
if [ info exists ::errorCode ] {
set save..."
(procedure "run_sim" line 74)
invoked from within
"run_sim run_sim_args_hash"
invoked from within
"if [ info exists ::errorCode ] {
set savedCode $::errorCode
set savedInfo $::errorInfo
error "$result" $savedInfo ..."
(procedure "run_eda_simulation_tool" line 334)
invoked from within
"run_eda_simulation_tool eda_opts_hash"

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/Lab1_testbench.v Executable file
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module Lab1_testbench();
reg [7:0] switch;
wire [7:0] hex;
Lab1 dut (hex, switch);
initial
switch <= 7'b0;
always begin
#10
switch <= switch + 7'b0000001;
end
initial begin
#1500 $stop;
end
endmodule

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/Lab1_testbench.v.bak Executable file
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module Lab1_testbench();
reg [7:0] switch;
wire [7:0] hex;
Lab1 dut (hex, switch);
initial
switch <= 7'b0;
always begin
#10
switch <= switch + 7'b0000001;
end
initial begin
#1500 $stop;
end
endmodule

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/db/Lab1.(0).cnf.cdb Executable file
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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/db/Lab1.cbx.xml Executable file
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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="Lab1">
</PROJECT>
</LOG_ROOT>

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/db/Lab1.db_info Executable file
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Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Version_Index = 486699264
Creation_Time = Thu Sep 15 16:25:23 2022

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/db/Lab1.hier_info Executable file
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|Lab1
HEX0[0] << SW[0].DB_MAX_OUTPUT_PORT_TYPE
HEX0[1] << SW[1].DB_MAX_OUTPUT_PORT_TYPE
HEX0[2] << SW[2].DB_MAX_OUTPUT_PORT_TYPE
HEX0[3] << SW[3].DB_MAX_OUTPUT_PORT_TYPE
HEX0[4] << SW[4].DB_MAX_OUTPUT_PORT_TYPE
HEX0[5] << SW[5].DB_MAX_OUTPUT_PORT_TYPE
HEX0[6] << SW[6].DB_MAX_OUTPUT_PORT_TYPE
HEX0[7] << SW[7].DB_MAX_OUTPUT_PORT_TYPE
SW[0] => HEX0[0].DATAIN
SW[1] => HEX0[1].DATAIN
SW[2] => HEX0[2].DATAIN
SW[3] => HEX0[3].DATAIN
SW[4] => HEX0[4].DATAIN
SW[5] => HEX0[5].DATAIN
SW[6] => HEX0[6].DATAIN
SW[7] => HEX0[7].DATAIN

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/db/Lab1.hif Executable file
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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/db/Lab1.lpc.html Executable file
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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/db/Lab1.lpc.rdb Executable file
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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/db/Lab1.lpc.txt Executable file
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/db/Lab1.map.ammdb Executable file
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v1

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1663273529645 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1663273529646 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 15 16:25:29 2022 " "Processing started: Thu Sep 15 16:25:29 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1663273529646 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1663273529646 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Lab1 -c Lab1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off Lab1 -c Lab1" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1663273529646 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1663273529807 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1663273529807 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Lab1.v 1 1 " "Found 1 design units, including 1 entities, in source file Lab1.v" { { "Info" "ISGN_ENTITY_NAME" "1 Lab1 " "Found entity 1: Lab1" { } { { "Lab1.v" "" { Text "/home/sharpe/Documents/projects/comp-arch/4RegisterFile/Lab1.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1663273536618 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1663273536618 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "Lab1_testbenc.v " "Can't analyze file -- file Lab1_testbenc.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1663273536618 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "Lab1 " "Elaborating entity \"Lab1\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1663273536652 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1663273536984 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1663273536984 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "16 " "Implemented 16 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1663273537018 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1663273537018 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1663273537018 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "922 " "Peak virtual memory: 922 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1663273537022 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 15 16:25:37 2022 " "Processing ended: Thu Sep 15 16:25:37 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1663273537022 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1663273537022 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:18 " "Total CPU time (on all processors): 00:00:18" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1663273537022 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1663273537022 ""}

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/db/Lab1.smart_action.txt Executable file
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FIT

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start_analysis_synthesis:s:00:00:09
start_analysis_elaboration:s

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/db/Lab1_partition_pins.json Executable file
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{
"partitions" : [
{
"name" : "Top",
"pins" : [
{
"name" : "HEX0[0]",
"strict" : false
},
{
"name" : "HEX0[1]",
"strict" : false
},
{
"name" : "HEX0[2]",
"strict" : false
},
{
"name" : "HEX0[3]",
"strict" : false
},
{
"name" : "HEX0[4]",
"strict" : false
},
{
"name" : "HEX0[5]",
"strict" : false
},
{
"name" : "HEX0[6]",
"strict" : false
},
{
"name" : "HEX0[7]",
"strict" : false
},
{
"name" : "SW[0]",
"strict" : false
},
{
"name" : "SW[1]",
"strict" : false
},
{
"name" : "SW[2]",
"strict" : false
},
{
"name" : "SW[3]",
"strict" : false
},
{
"name" : "SW[4]",
"strict" : false
},
{
"name" : "SW[5]",
"strict" : false
},
{
"name" : "SW[6]",
"strict" : false
},
{
"name" : "SW[7]",
"strict" : false
}
]
}
]
}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1662673690384 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1662673690385 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 8 17:48:10 2022 " "Processing started: Thu Sep 8 17:48:10 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1662673690385 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1662673690385 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Lab1 -c Lab1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off Lab1 -c Lab1" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1662673690385 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1662673690546 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1662673690546 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Lab1.v 1 1 " "Found 1 design units, including 1 entities, in source file Lab1.v" { { "Info" "ISGN_ENTITY_NAME" "1 Lab1 " "Found entity 1: Lab1" { } { { "Lab1.v" "" { Text "/home/sharpe/Documents/projects/comp-arch/4RegisterFile/Lab1.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1662673697474 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1662673697474 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "Lab1_testbenc.v " "Can't analyze file -- file Lab1_testbenc.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1662673697474 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "Lab1 " "Elaborating entity \"Lab1\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1662673697506 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1662673697831 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1662673697831 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "16 " "Implemented 16 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1662673697873 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1662673697873 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1662673697873 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "921 " "Peak virtual memory: 921 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1662673697877 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 8 17:48:17 2022 " "Processing ended: Thu Sep 8 17:48:17 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1662673697877 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1662673697877 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:19 " "Total CPU time (on all processors): 00:00:19" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1662673697877 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1662673697877 ""}

139
3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/devkits/DE10_LITE_Golden_Top/DE10_LITE_Golden_Top.v Executable file
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// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.1 :| Alexandra Du :| 06/01/2016:| Added Verilog file
// ============================================================================
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
`define ENABLE_ADC_CLOCK
`define ENABLE_CLOCK1
`define ENABLE_CLOCK2
`define ENABLE_SDRAM
`define ENABLE_HEX0
`define ENABLE_HEX1
`define ENABLE_HEX2
`define ENABLE_HEX3
`define ENABLE_HEX4
`define ENABLE_HEX5
`define ENABLE_KEY
`define ENABLE_LED
`define ENABLE_SW
`define ENABLE_VGA
`define ENABLE_ACCELEROMETER
`define ENABLE_ARDUINO
`define ENABLE_GPIO
module DE10_LITE_Golden_Top(
//////////// ADC CLOCK: 3.3-V LVTTL //////////
`ifdef ENABLE_ADC_CLOCK
input ADC_CLK_10,
`endif
//////////// CLOCK 1: 3.3-V LVTTL //////////
`ifdef ENABLE_CLOCK1
input MAX10_CLK1_50,
`endif
//////////// CLOCK 2: 3.3-V LVTTL //////////
`ifdef ENABLE_CLOCK2
input MAX10_CLK2_50,
`endif
//////////// SDRAM: 3.3-V LVTTL //////////
`ifdef ENABLE_SDRAM
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
`endif
//////////// SEG7: 3.3-V LVTTL //////////
`ifdef ENABLE_HEX0
output [7:0] HEX0,
`endif
`ifdef ENABLE_HEX1
output [7:0] HEX1,
`endif
`ifdef ENABLE_HEX2
output [7:0] HEX2,
`endif
`ifdef ENABLE_HEX3
output [7:0] HEX3,
`endif
`ifdef ENABLE_HEX4
output [7:0] HEX4,
`endif
`ifdef ENABLE_HEX5
output [7:0] HEX5,
`endif
//////////// KEY: 3.3 V SCHMITT TRIGGER //////////
`ifdef ENABLE_KEY
input [1:0] KEY,
`endif
//////////// LED: 3.3-V LVTTL //////////
`ifdef ENABLE_LED
output [9:0] LEDR,
`endif
//////////// SW: 3.3-V LVTTL //////////
`ifdef ENABLE_SW
input [9:0] SW,
`endif
//////////// VGA: 3.3-V LVTTL //////////
`ifdef ENABLE_VGA
output [3:0] VGA_B,
output [3:0] VGA_G,
output VGA_HS,
output [3:0] VGA_R,
output VGA_VS,
`endif
//////////// Accelerometer: 3.3-V LVTTL //////////
`ifdef ENABLE_ACCELEROMETER
output GSENSOR_CS_N,
input [2:1] GSENSOR_INT,
output GSENSOR_SCLK,
inout GSENSOR_SDI,
inout GSENSOR_SDO,
`endif
//////////// Arduino: 3.3-V LVTTL //////////
`ifdef ENABLE_ARDUINO
inout [15:0] ARDUINO_IO,
inout ARDUINO_RESET_N,
`endif
//////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL //////////
`ifdef ENABLE_GPIO
inout [35:0] GPIO
`endif
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
endmodule

3
3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/devkits/DE10_LITE_Golden_Top/filelist.txt Executable file
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platform_setup.tcl
filelist.txt
DE10_LITE_Golden_Top.v

429
3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/devkits/DE10_LITE_Golden_Top/platform_setup.tcl Executable file
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proc ::setup_project {} {
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 09:47:48 June 12, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# top_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10 FPGA"
set_global_assignment -name DEVICE 10M50DAF484C6GES
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50
set_location_assignment PIN_N5 -to ADC_CLK_10
set_location_assignment PIN_P11 -to MAX10_CLK1_50
set_location_assignment PIN_N14 -to MAX10_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
set_location_assignment PIN_U17 -to DRAM_ADDR[0]
set_location_assignment PIN_W19 -to DRAM_ADDR[1]
set_location_assignment PIN_V18 -to DRAM_ADDR[2]
set_location_assignment PIN_U18 -to DRAM_ADDR[3]
set_location_assignment PIN_U19 -to DRAM_ADDR[4]
set_location_assignment PIN_T18 -to DRAM_ADDR[5]
set_location_assignment PIN_T19 -to DRAM_ADDR[6]
set_location_assignment PIN_R18 -to DRAM_ADDR[7]
set_location_assignment PIN_P18 -to DRAM_ADDR[8]
set_location_assignment PIN_P19 -to DRAM_ADDR[9]
set_location_assignment PIN_T20 -to DRAM_ADDR[10]
set_location_assignment PIN_P20 -to DRAM_ADDR[11]
set_location_assignment PIN_R20 -to DRAM_ADDR[12]
set_location_assignment PIN_T21 -to DRAM_BA[0]
set_location_assignment PIN_T22 -to DRAM_BA[1]
set_location_assignment PIN_U21 -to DRAM_CAS_N
set_location_assignment PIN_N22 -to DRAM_CKE
set_location_assignment PIN_L14 -to DRAM_CLK
set_location_assignment PIN_U20 -to DRAM_CS_N
set_location_assignment PIN_Y21 -to DRAM_DQ[0]
set_location_assignment PIN_Y20 -to DRAM_DQ[1]
set_location_assignment PIN_AA22 -to DRAM_DQ[2]
set_location_assignment PIN_AA21 -to DRAM_DQ[3]
set_location_assignment PIN_Y22 -to DRAM_DQ[4]
set_location_assignment PIN_W22 -to DRAM_DQ[5]
set_location_assignment PIN_W20 -to DRAM_DQ[6]
set_location_assignment PIN_V21 -to DRAM_DQ[7]
set_location_assignment PIN_P21 -to DRAM_DQ[8]
set_location_assignment PIN_J22 -to DRAM_DQ[9]
set_location_assignment PIN_H21 -to DRAM_DQ[10]
set_location_assignment PIN_H22 -to DRAM_DQ[11]
set_location_assignment PIN_G22 -to DRAM_DQ[12]
set_location_assignment PIN_G20 -to DRAM_DQ[13]
set_location_assignment PIN_G19 -to DRAM_DQ[14]
set_location_assignment PIN_F22 -to DRAM_DQ[15]
set_location_assignment PIN_V22 -to DRAM_LDQM
set_location_assignment PIN_U22 -to DRAM_RAS_N
set_location_assignment PIN_J21 -to DRAM_UDQM
set_location_assignment PIN_V20 -to DRAM_WE_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7]
set_location_assignment PIN_C14 -to HEX0[0]
set_location_assignment PIN_E15 -to HEX0[1]
set_location_assignment PIN_C15 -to HEX0[2]
set_location_assignment PIN_C16 -to HEX0[3]
set_location_assignment PIN_E16 -to HEX0[4]
set_location_assignment PIN_D17 -to HEX0[5]
set_location_assignment PIN_C17 -to HEX0[6]
set_location_assignment PIN_D15 -to HEX0[7]
set_location_assignment PIN_C18 -to HEX1[0]
set_location_assignment PIN_D18 -to HEX1[1]
set_location_assignment PIN_E18 -to HEX1[2]
set_location_assignment PIN_B16 -to HEX1[3]
set_location_assignment PIN_A17 -to HEX1[4]
set_location_assignment PIN_A18 -to HEX1[5]
set_location_assignment PIN_B17 -to HEX1[6]
set_location_assignment PIN_A16 -to HEX1[7]
set_location_assignment PIN_B20 -to HEX2[0]
set_location_assignment PIN_A20 -to HEX2[1]
set_location_assignment PIN_B19 -to HEX2[2]
set_location_assignment PIN_A21 -to HEX2[3]
set_location_assignment PIN_B21 -to HEX2[4]
set_location_assignment PIN_C22 -to HEX2[5]
set_location_assignment PIN_B22 -to HEX2[6]
set_location_assignment PIN_A19 -to HEX2[7]
set_location_assignment PIN_F21 -to HEX3[0]
set_location_assignment PIN_E22 -to HEX3[1]
set_location_assignment PIN_E21 -to HEX3[2]
set_location_assignment PIN_C19 -to HEX3[3]
set_location_assignment PIN_C20 -to HEX3[4]
set_location_assignment PIN_D19 -to HEX3[5]
set_location_assignment PIN_E17 -to HEX3[6]
set_location_assignment PIN_D22 -to HEX3[7]
set_location_assignment PIN_F18 -to HEX4[0]
set_location_assignment PIN_E20 -to HEX4[1]
set_location_assignment PIN_E19 -to HEX4[2]
set_location_assignment PIN_J18 -to HEX4[3]
set_location_assignment PIN_H19 -to HEX4[4]
set_location_assignment PIN_F19 -to HEX4[5]
set_location_assignment PIN_F20 -to HEX4[6]
set_location_assignment PIN_F17 -to HEX4[7]
set_location_assignment PIN_J20 -to HEX5[0]
set_location_assignment PIN_K20 -to HEX5[1]
set_location_assignment PIN_L18 -to HEX5[2]
set_location_assignment PIN_N18 -to HEX5[3]
set_location_assignment PIN_M20 -to HEX5[4]
set_location_assignment PIN_N19 -to HEX5[5]
set_location_assignment PIN_N20 -to HEX5[6]
set_location_assignment PIN_L19 -to HEX5[7]
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1]
set_location_assignment PIN_B8 -to KEY[0]
set_location_assignment PIN_A7 -to KEY[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
set_location_assignment PIN_A8 -to LEDR[0]
set_location_assignment PIN_A9 -to LEDR[1]
set_location_assignment PIN_A10 -to LEDR[2]
set_location_assignment PIN_B10 -to LEDR[3]
set_location_assignment PIN_D13 -to LEDR[4]
set_location_assignment PIN_C13 -to LEDR[5]
set_location_assignment PIN_E14 -to LEDR[6]
set_location_assignment PIN_D14 -to LEDR[7]
set_location_assignment PIN_A11 -to LEDR[8]
set_location_assignment PIN_B11 -to LEDR[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
set_location_assignment PIN_C10 -to SW[0]
set_location_assignment PIN_C11 -to SW[1]
set_location_assignment PIN_D12 -to SW[2]
set_location_assignment PIN_C12 -to SW[3]
set_location_assignment PIN_A12 -to SW[4]
set_location_assignment PIN_B12 -to SW[5]
set_location_assignment PIN_A13 -to SW[6]
set_location_assignment PIN_A14 -to SW[7]
set_location_assignment PIN_B14 -to SW[8]
set_location_assignment PIN_F15 -to SW[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
set_location_assignment PIN_P1 -to VGA_B[0]
set_location_assignment PIN_T1 -to VGA_B[1]
set_location_assignment PIN_P4 -to VGA_B[2]
set_location_assignment PIN_N2 -to VGA_B[3]
set_location_assignment PIN_W1 -to VGA_G[0]
set_location_assignment PIN_T2 -to VGA_G[1]
set_location_assignment PIN_R2 -to VGA_G[2]
set_location_assignment PIN_R1 -to VGA_G[3]
set_location_assignment PIN_N3 -to VGA_HS
set_location_assignment PIN_AA1 -to VGA_R[0]
set_location_assignment PIN_V1 -to VGA_R[1]
set_location_assignment PIN_Y2 -to VGA_R[2]
set_location_assignment PIN_Y1 -to VGA_R[3]
set_location_assignment PIN_N1 -to VGA_VS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO
set_location_assignment PIN_AB16 -to GSENSOR_CS_N
set_location_assignment PIN_Y14 -to GSENSOR_INT[1]
set_location_assignment PIN_Y13 -to GSENSOR_INT[2]
set_location_assignment PIN_AB15 -to GSENSOR_SCLK
set_location_assignment PIN_V11 -to GSENSOR_SDI
set_location_assignment PIN_V12 -to GSENSOR_SDO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
set_location_assignment PIN_AB5 -to ARDUINO_IO[0]
set_location_assignment PIN_AB6 -to ARDUINO_IO[1]
set_location_assignment PIN_AB7 -to ARDUINO_IO[2]
set_location_assignment PIN_AB8 -to ARDUINO_IO[3]
set_location_assignment PIN_AB9 -to ARDUINO_IO[4]
set_location_assignment PIN_Y10 -to ARDUINO_IO[5]
set_location_assignment PIN_AA11 -to ARDUINO_IO[6]
set_location_assignment PIN_AA12 -to ARDUINO_IO[7]
set_location_assignment PIN_AB17 -to ARDUINO_IO[8]
set_location_assignment PIN_AA17 -to ARDUINO_IO[9]
set_location_assignment PIN_AB19 -to ARDUINO_IO[10]
set_location_assignment PIN_AA19 -to ARDUINO_IO[11]
set_location_assignment PIN_Y19 -to ARDUINO_IO[12]
set_location_assignment PIN_AB20 -to ARDUINO_IO[13]
set_location_assignment PIN_AB21 -to ARDUINO_IO[14]
set_location_assignment PIN_AA20 -to ARDUINO_IO[15]
set_location_assignment PIN_F16 -to ARDUINO_RESET_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35]
set_location_assignment PIN_V10 -to GPIO[0]
set_location_assignment PIN_W10 -to GPIO[1]
set_location_assignment PIN_V9 -to GPIO[2]
set_location_assignment PIN_W9 -to GPIO[3]
set_location_assignment PIN_V8 -to GPIO[4]
set_location_assignment PIN_W8 -to GPIO[5]
set_location_assignment PIN_V7 -to GPIO[6]
set_location_assignment PIN_W7 -to GPIO[7]
set_location_assignment PIN_W6 -to GPIO[8]
set_location_assignment PIN_V5 -to GPIO[9]
set_location_assignment PIN_W5 -to GPIO[10]
set_location_assignment PIN_AA15 -to GPIO[11]
set_location_assignment PIN_AA14 -to GPIO[12]
set_location_assignment PIN_W13 -to GPIO[13]
set_location_assignment PIN_W12 -to GPIO[14]
set_location_assignment PIN_AB13 -to GPIO[15]
set_location_assignment PIN_AB12 -to GPIO[16]
set_location_assignment PIN_Y11 -to GPIO[17]
set_location_assignment PIN_AB11 -to GPIO[18]
set_location_assignment PIN_W11 -to GPIO[19]
set_location_assignment PIN_AB10 -to GPIO[20]
set_location_assignment PIN_AA10 -to GPIO[21]
set_location_assignment PIN_AA9 -to GPIO[22]
set_location_assignment PIN_Y8 -to GPIO[23]
set_location_assignment PIN_AA8 -to GPIO[24]
set_location_assignment PIN_Y7 -to GPIO[25]
set_location_assignment PIN_AA7 -to GPIO[26]
set_location_assignment PIN_Y6 -to GPIO[27]
set_location_assignment PIN_AA6 -to GPIO[28]
set_location_assignment PIN_Y5 -to GPIO[29]
set_location_assignment PIN_AA5 -to GPIO[30]
set_location_assignment PIN_Y4 -to GPIO[31]
set_location_assignment PIN_AB3 -to GPIO[32]
set_location_assignment PIN_Y3 -to GPIO[33]
set_location_assignment PIN_AB2 -to GPIO[34]
set_location_assignment PIN_AA2 -to GPIO[35]
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE DE10_LITE_Golden_Top.v
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
}

6
3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/devkits/DE10_LITE_Golden_Top/qar_info.json Executable file
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{
"common_dir" : "/data/adu/17.0/Lite/Max10/Max_10_DE10_LITE/DE10_LITE_Golden_Top_project/",
"acds_version" : "Version 17.0.0",
"platform" : "linux",
"os" : "Red Hat"
}

8
3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/devkits/readme.txt Executable file
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This devkits directory contains development kit baseline example designs.
HOW TO SETUP PIN ASSIGNMENTS
1) Bring up the Tcl Console panel in Quartus from the View menu --> Utility Windows.
2) Type command 'source platform_setup.tcl' in the Tcl console.
3) Type command 'setup_project' in the Tcl console.
- Running this command will populate all assignments available in the setup_platform.tcl to your project QSF file.

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/incremental_db/README Executable file
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This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

3
3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/incremental_db/compiled_partitions/Lab1.db_info Executable file
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Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Version_Index = 486699264
Creation_Time = Thu Sep 8 17:48:17 2022

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/incremental_db/compiled_partitions/Lab1.root_partition.map.hbdb.sig Executable file
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fa8634a97a99232bb4bb1c2e0a376209

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/output_files/Lab1.done Executable file
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Thu Sep 15 16:25:37 2022

126
3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/output_files/Lab1.flow.rpt Executable file
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Flow report for Lab1
Thu Sep 15 16:25:37 2022
Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Thu Sep 15 16:25:37 2022 ;
; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
; Revision Name ; Lab1 ;
; Top-level Entity Name ; Lab1 ;
; Family ; MAX 10 ;
; Device ; 10M50DAF484C6GES ;
; Timing Models ; Preliminary ;
; Total logic elements ; 0 ;
; Total combinational functions ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 16 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
; UFM blocks ; 0 ;
; ADC blocks ; 0 ;
+------------------------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/15/2022 16:25:29 ;
; Main task ; Compilation ;
; Revision Name ; Lab1 ;
+-------------------+---------------------+
+------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+--------------------------------------+----------------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+--------------------------------------+----------------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 97221505579788.166327352928691 ; -- ; -- ; -- ;
; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; Lab1_testbench ;
; EDA_NATIVELINK_SIMULATION_TEST_BENCH ; Lab1_testbench ; -- ; -- ; eda_simulation ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;
; EDA_TEST_BENCH_ENABLE_STATUS ; TEST_BENCH_MODE ; -- ; -- ; eda_simulation ;
; EDA_TEST_BENCH_FILE ; Lab1_testbench.v ; -- ; -- ; Lab1_testbench ;
; EDA_TEST_BENCH_MODULE_NAME ; Lab1_testbench ; -- ; -- ; Lab1_testbench ;
; EDA_TEST_BENCH_NAME ; Lab1_testbench ; -- ; -- ; eda_simulation ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+--------------------------------------+----------------------------------------+---------------+-------------+----------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 874 MB ; 00:00:18 ;
; Total ; 00:00:07 ; -- ; -- ; 00:00:18 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+--------------------------+----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+--------------------------+----------+------------+----------------+
; Analysis & Synthesis ; sharpe-ThinkPad-P1-Gen-3 ; Zorin OS ; 16 ; x86_64 ;
+----------------------+--------------------------+----------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off Lab1 -c Lab1

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3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/output_files/Lab1.map.rpt Executable file
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Analysis & Synthesis report for Lab1
Thu Sep 15 16:25:37 2022
Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Post-Synthesis Netlist Statistics for Top Partition
10. Elapsed Time Per Partition
11. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 15 16:25:37 2022 ;
; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
; Revision Name ; Lab1 ;
; Top-level Entity Name ; Lab1 ;
; Family ; MAX 10 ;
; Total logic elements ; 0 ;
; Total combinational functions ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 16 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
; UFM blocks ; 0 ;
; ADC blocks ; 0 ;
+------------------------------------+---------------------------------------------+
+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------------------+--------------------+--------------------+
; Device ; 10M50DAF484C6GES ; ;
; Top-level entity name ; Lab1 ; Lab1 ;
; Family name ; MAX 10 ; Cyclone V ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
+------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 6 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
+----------------------------+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------------------+---------+
; Lab1.v ; yes ; User Verilog HDL File ; /home/sharpe/Documents/projects/comp-arch/4RegisterFile/Lab1.v ; ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------------------+---------+
+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; ; ;
; Total combinational functions ; 0 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 0 ;
; -- <=2 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 0 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 16 ;
; ; ;
; Embedded Multiplier 9-bit elements ; 0 ;
; ; ;
; Maximum fan-out node ; HEX0[0]~output ;
; Maximum fan-out ; 1 ;
; Total fan-out ; 24 ;
; Average fan-out ; 0.75 ;
+---------------------------------------------+----------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+
; |Lab1 ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; |Lab1 ; Lab1 ; work ;
+----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-------------------+---------------------------------+
; Type ; Count ;
+-------------------+---------------------------------+
; boundary_port ; 16 ;
; ; ;
; Max LUT depth ; 0.00 ;
; Average LUT depth ; 0.00 ;
+-------------------+---------------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:00 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Info: Processing started: Thu Sep 15 16:25:29 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Lab1 -c Lab1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file Lab1.v
Info (12023): Found entity 1: Lab1 File: /home/sharpe/Documents/projects/comp-arch/4RegisterFile/Lab1.v Line: 1
Warning (12019): Can't analyze file -- file Lab1_testbenc.v is missing
Info (12127): Elaborating entity "Lab1" for the top level hierarchy
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 16 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 8 input pins
Info (21059): Implemented 8 output pins
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 922 megabytes
Info: Processing ended: Thu Sep 15 16:25:37 2022
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:18

16
3rd-Semester-Fall-2022/Comp-Arch/4RegisterFile/output_files/Lab1.map.summary Executable file
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Analysis & Synthesis Status : Successful - Thu Sep 15 16:25:37 2022
Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Revision Name : Lab1
Top-level Entity Name : Lab1
Family : MAX 10
Total logic elements : 0
Total combinational functions : 0
Dedicated logic registers : 0
Total registers : 0
Total pins : 16
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0
UFM blocks : 0
ADC blocks : 0

30
3rd-Semester-Fall-2022/Comp-Arch/Lab2/Lab2.qpf Executable file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 16:12:48 September 15, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.1"
DATE = "16:12:48 September 15, 2022"
# Revisions
PROJECT_REVISION = "Lab2"

53
3rd-Semester-Fall-2022/Comp-Arch/Lab2/Lab2.qsf Executable file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 16:12:48 September 15, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Lab2_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M08DAF484C8G
set_global_assignment -name TOP_LEVEL_ENTITY Lab2
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:12:48 SEPTEMBER 15, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

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3rd-Semester-Fall-2022/Comp-Arch/Lab2/db/Lab2.db_info Executable file
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Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Version_Index = 486699264
Creation_Time = Thu Sep 15 16:12:48 2022

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3rd-Semester-Fall-2022/Comp-Arch/RISCV32I_Assembler.py Executable file
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f7s = {
'ADD': 0,
'SUB': 32,
'AND': 0,
'OR': 0,
'XOR': 0,
}
f3s = {
'ADD': 0,
'SUB': 0,
'AND': 7,
'OR': 6,
'XOR': 4,
}
opcodes = {
'ADD': 51,
'SUB': 51,
'AND': 51,
'OR': 51,
'XOR': 51,
}
print('Separate all arguments with spaces ONLY.')
for x in range(10):
asm = input(f'I{x}: ').split()
if asm[0] in ('ADD', 'SUB', 'XOR', 'OR', 'AND'):
rd = eval(asm[1]) << 7
rs1 = eval(asm[2]) << 15
rs2 = eval(asm[3]) << 20
f7 = f7s[asm[0]] << 25
f3 = f3s[asm[0]] << 12
opcode = opcodes[asm[0]]
inst = f7 + rs2 + rs1 + f3 + rd + opcode
bininst = bin(inst)
bininst = bininst[:2] + '0'*(30-len(bininst)) + bininst[2:]
hexinst = hex(inst)
hexinst = hexinst[:2] + '0'*(7-len(hexinst)) + hexinst[2:]
print(bininst)
print(hexinst)

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3rd-Semester-Fall-2022/PDS/.vscode/c_cpp_properties.json vendored Executable file
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{
"configurations": [
{
"name": "Linux",
"includePath": [
"${workspaceFolder}/**"
],
"defines": [],
"compilerPath": "/usr/bin/gcc",
"cStandard": "gnu17",
"cppStandard": "c++17",
"intelliSenseMode": "linux-gcc-x64",
"configurationProvider": "ms-vscode.makefile-tools"
}
],
"version": 4
}

7
3rd-Semester-Fall-2022/PDS/.vscode/launch.json vendored Executable file
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{
// Use IntelliSense to learn about possible attributes.
// Hover to view descriptions of existing attributes.
// For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
"version": "0.2.0",
"configurations": []
}

33
3rd-Semester-Fall-2022/PDS/.vscode/settings.json vendored Executable file
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{
"files.associations": {
"*.tcc": "cpp",
"cctype": "cpp",
"clocale": "cpp",
"cmath": "cpp",
"compare": "cpp",
"concepts": "cpp",
"cstdint": "cpp",
"cstdio": "cpp",
"cstdlib": "cpp",
"cwchar": "cpp",
"cwctype": "cpp",
"vector": "cpp",
"exception": "cpp",
"initializer_list": "cpp",
"iosfwd": "cpp",
"iostream": "cpp",
"istream": "cpp",
"limits": "cpp",
"new": "cpp",
"numbers": "cpp",
"ostream": "cpp",
"stdexcept": "cpp",
"streambuf": "cpp",
"string": "cpp",
"string_view": "cpp",
"system_error": "cpp",
"type_traits": "cpp",
"typeinfo": "cpp",
"fstream": "cpp"
}
}

28
3rd-Semester-Fall-2022/PDS/.vscode/tasks.json vendored Executable file
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{
"tasks": [
{
"type": "cppbuild",
"label": "C/C++: g++ build active file",
"command": "/usr/bin/g++",
"args": [
"-fdiagnostics-color=always",
"-g",
"${file}",
"-o",
"${fileDirname}/${fileBasenameNoExtension}"
],
"options": {
"cwd": "${fileDirname}"
},
"problemMatcher": [
"$gcc"
],
"group": {
"kind": "build",
"isDefault": true
},
"detail": "Task generated by Debugger."
}
],
"version": "2.0.0"
}

5
3rd-Semester-Fall-2022/PDS/Homework01/.vscode/settings.json vendored Executable file
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{
"files.associations": {
"ostream": "cpp"
}
}

47
3rd-Semester-Fall-2022/PDS/Homework01/HW01_Aidan_Sharpe.cpp Executable file
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/****************************************************************
* Name: Aidan Sharpe
* Course: Principles of Data Structures
* Class: CS04225
* Assignment Date: September 19, 2022
* File Name: HW01_Aidan_Sharpe.cpp
*****************************************************************
* ID: Homework 1 Problem 1
* Purpose: Recieve and perform an operation on 5 numbers
*****************************************************************/
#include <iostream>
#include <string>
#define ENTRIES 5
int main()
{
std::string entry;
int nums[ENTRIES];
int sum = 0, max, min;
// get entries
for(int i = 0; i < ENTRIES; i++)
{
std::cout << "Enter int (" << i+1 << "):\n";
std::cin >> entry;
nums[i] = std::stoi(entry);
}
min = nums[0];
max = nums[0];
std::cout << "Values Entered:";
for(int i = 0; i < ENTRIES; i++)
{
std::cout << " " << nums[i]; // repeat entries
min = (nums[i] < min) ? nums[i] : min; // update min to current min
max = (nums[i] > max) ? nums[i] : max; // update max to current max
sum += nums[i];
}
std::cout << "\nSUM:\t" << sum << std::endl;
std::cout << "MAX:\t" << max << std::endl;
std::cout << "MIN:\t" << min << std::endl;
std::cout << "AVG:\t" << (float)sum / ENTRIES << std::endl;
return 0;
}

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3rd-Semester-Fall-2022/PDS/Homework02/.vscode/tasks.json vendored Executable file
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{
"tasks": [
{
"type": "cppbuild",
"label": "C/C++: g++ build active file",
"command": "/usr/bin/g++",
"args": [
"-fdiagnostics-color=always",
"-g",
"${file}",
"-o",
"${fileDirname}/${fileBasenameNoExtension}"
],
"options": {
"cwd": "${fileDirname}"
},
"problemMatcher": [
"$gcc"
],
"group": {
"kind": "build",
"isDefault": true
},
"detail": "Task generated by Debugger."
}
],
"version": "2.0.0"
}

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3rd-Semester-Fall-2022/PDS/Homework02/HW02_Aidan_Sharpe.cpp Executable file
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/****************************************************************
* Name: Aidan Sharpe
* Course: Principles of Data Structures
* Class: CS04225
* Assignment Date: September 23, 2022
* File Name: HW02_Aidan_Sharpe.cpp
*****************************************************************
* ID: Homework 2 Problem 1
* Purpose: Sort and search through a vector of ints
*****************************************************************/
#include <iostream>
#include <vector>
/// @brief Sort an incoming vector via selection sort
/// @param vals Vector of random integers
/// @return Original values sorted in ascending order
std::vector<int> vectorSelectionSort(std::vector<int> vals);
/// @brief Find val in vals with linear search
/// @param val number to find
/// @param vals ints to look through
/// @return {index, # of comparisons}
std::vector<int> vecIntLinearSearch(int val, std::vector<int> vals);
/// @brief Find val in vals with binary search
/// @param val number to find
/// @param vals ints to look through
/// @return {index, # of comparisons}
std::vector<int> vecIntBinarySearch(int val, std::vector<int> vals);
/// @brief print a vector of ints
/// @param vals vector to print
/// @param isSorted whether or not the vector is known to be sorted
void printVecInt(std::vector<int> vals, bool isSorted);
int main()
{
std::vector<int> vals{
8284, 4663, 5670, 2284, 1197,
9109, 6547, 7652, 7925, 2421,
8717, 6976, 1671, 5533, 1170,
1112, 4921, 9702, 4177, 9821,
2454, 3211, 5594, 2417, 7294
};
printVecInt(vals, false);
vals = vectorSelectionSort(vals);
printVecInt(vals, true);
int sel;
std::cout << "Query a number:\n";
std::cin >> sel;
std::vector<int> linearS = vecIntLinearSearch(sel, vals);
if (linearS[0] >= 0)
std::cout << "Value " << sel << " was found with linear search at index " << linearS[0] << " with " << linearS[1]<< " comparisons.\n";
else
std::cout << "Linear search could not find " << sel << " after " << linearS[1] << " comparisons\n";
std::vector<int> binaryS = vecIntBinarySearch(sel, vals);
if (binaryS[0] >= 0)
std::cout << "Value " << sel << " was found with binary search at index " << binaryS[0] << " with " << binaryS[1]<< " comparisons.\n";
else
std::cout << "Binary search could not find " << sel << " after " << binaryS[1] << " comparisons\n";
return 0;
}
std::vector<int> vectorSelectionSort(std::vector<int> vals)
{
int temp; // throw-away variable for swapping
int mindex = 0; // index of the smallest number
for (int i = 0; i < vals.size() - 1; i++)
{
mindex = i;
// find index of smallest element
for (int j = i; j < vals.size(); j++)
if (vals[j] < vals[mindex])
mindex = j;
// swap element at i with smallest element
if (mindex > i)
{
temp = vals[mindex];
vals[mindex] = vals[i];
vals[i] = temp;
}
}
return vals;
}
void printVecInt(std::vector<int> vals, bool isSorted)
{
const int COLS = 5;
std::cout << "Values (" << ((isSorted) ? "" : "un") << "sorted):\n";
for (int i = 0; i < vals.size() / COLS + 1; i++)
{
for (int j = 0; j < COLS && i*COLS + j < vals.size(); j++)
std::cout << vals[i*COLS + j] << ", ";
std::cout << std::endl;
}
}
std::vector<int> vecIntLinearSearch(int val, std::vector<int> vals)
{
for (int i = 0; i < vals.size(); i++)
{
if (val == vals[i])
return std::vector<int>{i, i};
}
return std::vector<int>{-1, (int)vals.size()};
}
std::vector<int> vecIntBinarySearch(int val, std::vector<int> vals)
{
int min = 0, mid = (int)vals.size()/2, max = (int)vals.size() - 1;
bool found = false;
int comps = 0;
while (min != max)
{
comps++;
// short circuit find
if (vals[mid] == val)
return std::vector<int>{mid, comps};
// shrink search space to top half of remaining set
else if (vals[mid] < val)
{
min = mid + 1;
mid = (max + min)/2;
}
// shrink search space to bottom half of remaining set
else
{
max = mid - 1;
mid = (max + min)/2;
}
}
// if val is at the last remaining position, it has been found; else it has been proven to not be in the list
return (vals[mid] == val) ? std::vector<int>{mid, comps} : std::vector<int>{-1, comps};
}

5
3rd-Semester-Fall-2022/PDS/Homework03/.vscode/settings.json vendored Executable file
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{
"files.associations": {
"string": "cpp"
}
}

28
3rd-Semester-Fall-2022/PDS/Homework03/.vscode/tasks.json vendored Executable file
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@ -0,0 +1,28 @@
{
"tasks": [
{
"type": "cppbuild",
"label": "C/C++: g++ build active file",
"command": "/usr/bin/g++",
"args": [
"-fdiagnostics-color=always",
"-g",
"${file}",
"-o",
"${fileDirname}/${fileBasenameNoExtension}"
],
"options": {
"cwd": "${fileDirname}"
},
"problemMatcher": [
"$gcc"
],
"group": {
"kind": "build",
"isDefault": true
},
"detail": "Task generated by Debugger."
}
],
"version": "2.0.0"
}

BIN
3rd-Semester-Fall-2022/PDS/Homework03/Bottle Rocket Wk 3 physics slides (2).pdf Executable file
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BIN
3rd-Semester-Fall-2022/PDS/Homework03/HW03_Aidan_Sharpe Executable file
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110
3rd-Semester-Fall-2022/PDS/Homework03/HW03_Aidan_Sharpe.cpp Executable file
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@ -0,0 +1,110 @@
/****************************************************************
* Name: Aidan Sharpe
* Course: Principles of Data Structures
* Class: CS04225
* Assignment Date: October 10, 2022
* File Name: HW03_Aidan_Sharpe.cpp
*****************************************************************
* ID: Homework 3 Problem 1
* Purpose: Read, sort and write, ints from text files
*****************************************************************/
#include <iostream>
#include <fstream>
#include <string>
/// @brief sort a dynamically allocated array in-place
/// @param arrptr pointer to first element in dynamically allocated array
/// @param len length of dynamically allocated array
/// @return true if the array was sorted successfully
bool dynamicArraySelectionSort(int *arrptr, int len);
int main()
{
std::string fname;
std::string line;
std::ifstream readfile;
std::ofstream writefile;
std::cout << "Input file name:\n";
std::cin >> fname;
readfile.open(fname);
std::getline(readfile, line);
int num_count = std::stoi(line);
std::cout << "Reading " << num_count << " numbers...\n";
int *nums_ptr;
nums_ptr = new int[num_count];
// read numbers from file
// numbers are multi-digit and separated by either a space or newline char
int idx = 0;
while (std::getline(readfile, line))
{
std::string snum;
for (char c : line)
{
if (isdigit(c))
snum.push_back(c);
else if (c == ' ' || c == '\n')
{
*(nums_ptr + idx) = std::stoi(snum);
snum = "";
idx++;
}
}
}
readfile.close();
std::cout << "Done reading values.\n";
// sort numbers
std::cout << "Sorting values...\n";
dynamicArraySelectionSort(nums_ptr, num_count);
std::cout << "Enter filename for sorted values:\n";
std::cin >> fname;
writefile.open(fname);
// write sorted nums to file with 8 columns
std::cout << "Writing values to " << fname << "...\n";
for (int i = 0; i < num_count/8 + 1; i++)
{
for (int j = 0; j < 8 && i*8 + j < num_count; j++)
writefile << *(nums_ptr + i*8 + j) << " ";
writefile << "\n";
}
writefile.close();
std::cout << "Done writing values.\n";
// clear dynamically allocated pointers
delete [] nums_ptr;
nums_ptr = nullptr;
return 0;
}
bool dynamicArraySelectionSort(int *arrptr, int len)
{
int temp; // throw-away variable for swapping
int mindex = 0; // index of the smallest number
for (int i = 0; i < len - 1; i++)
{
mindex = i;
// find index of smallest element
for (int j = i; j < len; j++)
if (*(arrptr + j) < *(arrptr + mindex))
mindex = j;
// swap element at i with smallest element
if (mindex > i)
{
temp = *(arrptr + mindex);
*(arrptr + mindex) = *(arrptr + i);
*(arrptr + i) = temp;
}
}
return true;
}

61
3rd-Semester-Fall-2022/PDS/Homework03/HW03_input1.txt Executable file
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@ -0,0 +1,61 @@
1200
7208 77654 85070 28533 87834 22178 52619 85517 19695 3458 32378 17737 72813 72802 68711 69388 80828 17885 4353 24392
39248 72336 83773 32282 28494 21754 720 17880 85790 72018 36274 9350 66024 31344 37884 63858 53523 6855 59375 73218
10314 1753 7307 89479 80907 76019 75219 78087 3904 79572 12479 49505 68260 12605 88139 6755 34359 88859 30987 36502
77229 73613 52204 53253 14958 88 27111 74833 13296 2838 64403 23610 4592 71711 29441 1851 64082 14661 79939 74338
10585 8770 33843 78846 27727 31982 1953 68439 30841 32940 14941 24422 16554 67145 77675 37864 73586 21138 22697 86882
23977 3452 26844 34921 75163 62637 36772 55597 77298 33063 39936 87884 48186 73779 76730 75913 15762 78683 60704 52955
27975 75645 77378 50881 59143 65053 88745 49081 86192 27794 52315 26521 31247 85511 61442 22762 58148 14566 78360 45447
53982 34648 49683 12168 18427 42765 4433 34189 37800 65138 87145 65775 57135 74523 26657 32630 55928 31754 81711 58472
59549 50378 84993 7148 45889 56435 36262 14038 77354 30974 65837 41336 65622 25520 59856 84050 68285 64289 34591 16085
45779 38088 88212 19267 28963 24869 51897 84892 56624 49961 53364 32525 10339 54710 39673 62581 27497 82287 76619 14851
23262 52456 56187 88884 84328 26043 89286 62613 6685 33878 85050 58816 71966 83262 78083 10930 24484 46333 12174 87460
12646 71890 29985 22985 36600 76010 1918 64098 68297 78537 78949 7911 47345 51489 13148 41673 77532 12434 20638 569
52664 22040 59386 40983 21655 53821 58265 46139 16506 70439 43599 29152 52329 79936 58490 5282 72298 60408 69380 50595
48946 64681 64859 12643 26170 84359 60669 20055 6793 87659 20624 65810 19700 86362 23145 41355 50184 81410 3846 66690
68201 47445 5843 36882 43733 70685 42164 26031 41093 27896 82978 6391 2578 57837 19035 28748 52196 79704 55155 65342
77363 75780 47504 13415 72142 70649 54770 38678 68411 58616 21721 52964 22413 33916 89846 72498 14601 48363 8529 55694
76259 7860 62086 85189 72049 87473 30290 40598 77177 85445 22292 70892 71225 69796 84308 59720 56797 55430 14750 41560
30399 36471 4524 59164 70387 4370 41663 84988 52733 56544 50683 45345 64404 29121 40534 46454 26594 70824 87052 20123
72622 19344 1015 53847 5492 1675 29919 68641 57106 51022 20201 87505 87493 24725 56669 67881 35447 8332 69221 4533
71229 36256 49878 45633 65377 6764 8439 8323 83941 5491 28446 66563 31187 35814 36762 43031 37489 66682 21672 10947
34056 48225 8452 31549 72950 71474 15782 24750 86158 85004 29283 67387 37612 85513 29373 19342 2277 37812 27665 86218
49656 62464 69133 87195 14630 15896 40227 58471 88930 68251 69419 32986 26477 84223 64535 15779 72049 86670 40529 68208
88026 69812 45595 35638 71677 74968 54980 73955 29133 88998 76525 78789 67814 55659 75984 88796 71555 26211 57267 70485
10815 43038 19823 37292 43614 84358 53071 25663 87380 3601 10223 85406 79765 55819 31045 61443 47139 2377 51750 76272
7727 38275 71413 81893 10286 57398 80689 88193 89961 54309 68678 10776 13699 4853 54420 63665 5564 17492 89329 2944
27445 9552 88351 23562 71723 35748 85005 35215 44477 53107 27839 58557 7735 9253 50450 18021 73003 47492 16215 79316
18153 1245 93 38204 6099 54513 11870 11663 78357 17551 20959 15802 33455 25662 39365 15179 61410 40722 56746 22240
10182 84585 80797 17917 10190 47599 35938 89545 5091 58505 78862 29596 59751 85307 67801 72202 49820 79671 217 44530
7222 21176 66684 47029 46839 22401 62208 24601 63124 35306 53193 73306 36244 43990 7575 46434 1590 43513 45980 13033
18371 34842 42630 84474 36501 20431 66676 86321 16454 73245 47203 30028 10773 23888 77057 57612 46289 55618 88566 25765
924 51759 15423 37168 12102 22998 89955 20044 72864 52287 33077 1235 3481 82059 85709 39982 18842 68737 42655 41648
51982 89859 71676 62755 23747 65086 36720 76388 30704 41638 12154 37980 9749 27577 81501 21851 50576 81456 41895 33440
50095 81325 34675 53576 73384 36736 3558 8579 15473 52565 50227 73807 52424 31904 52914 82523 13342 89634 68912 50398
47624 81066 88378 57374 24995 86231 79225 75571 84039 37473 25363 44134 28798 60038 14062 18534 13126 17620 27113 34951
70186 77341 18758 38962 25597 78025 31486 38939 84011 16750 89337 41636 14168 4067 9010 39163 299 4587 24735 84338
42060 50098 44825 70858 26489 58887 5745 45967 76508 32858 80919 63046 20199 16029 18360 45796 4054 56198 1087 88066
72948 424 39702 87116 10844 55064 36280 11143 59651 67367 11833 18064 33817 56658 5274 60306 25546 11019 22626 18406
43878 13545 81452 70429 29574 16164 32578 39981 72363 33665 38047 55311 40442 84101 52428 51286 49165 5060 68781 25168
72427 80614 43232 16244 47273 48507 82903 72819 65878 15529 1225 19756 35426 89029 6538 71352 21545 39116 21333 3908
79133 65732 59220 35927 59833 28000 87213 25350 33060 72346 50519 21839 62961 10103 44435 26586 64962 37338 9405 40841
59219 16982 66949 4645 22363 73487 82350 43908 22603 13683 47817 18089 85768 23389 54016 55601 57741 57582 87304 7153
39928 54175 28992 19241 64278 73427 45827 45593 27118 61584 86434 86337 78566 69735 7335 17281 53223 89685 61190 82178
19720 25359 10267 15488 55100 70636 77442 29193 38218 74746 36346 84498 45273 71690 13740 25903 61469 59567 71496 4939
37504 74282 1277 26070 54018 14964 49704 17241 21001 20894 15771 40721 52605 26039 62562 24057 13027 56356 53250 57597
41102 5948 52095 86375 77638 72187 28630 49107 48107 10127 54047 85611 84409 61676 28033 54779 82992 77737 72020 20345
14983 87792 67418 67588 30183 39980 7997 49562 6336 67599 17159 53790 73547 69254 56517 61185 57794 85148 26645 15901
11627 87044 11512 6036 65072 39545 67168 64416 27283 49188 84761 48618 53332 62179 26207 89867 18512 40556 49429 24848
18156 72940 84991 1703 52195 51508 69241 19989 53008 12238 42242 64635 15634 60106 77024 87058 9651 54192 61474 43286
19732 62587 1905 79417 34766 34464 85636 53278 81372 51418 84479 9528 34358 85822 17584 2905 47330 3177 29246 16691
15415 71488 81326 31049 41594 74702 34459 57598 38894 5933 17236 64979 68520 25493 60748 19638 59957 56384 79269 57682
17802 73748 67210 58513 69570 1146 61418 33252 4323 665 49943 19738 78505 47622 57139 30100 32324 1598 4050 77571
13883 21286 58902 88755 53132 29650 18394 29441 2386 14015 87123 26541 4115 70686 85054 80037 71832 62824 23289 76156
63489 79585 12246 58347 43559 75738 4799 82235 83688 8849 76158 7572 36487 45060 12679 89619 81062 31073 29061 83449
51440 32536 26342 55555 13222 21396 45592 85055 84220 75234 71211 64062 64819 89809 32409 24730 75547 43560 23317 69236
58761 9476 83160 5248 60888 5839 11220 51951 43265 46633 51752 4705 79169 78094 60261 2392 15842 15853 3799 10062
1087 81362 80476 72258 81171 29237 13340 66719 72797 36658 52307 41558 46134 45467 53159 17022 51306 70731 75325 4571
27364 43429 15629 22885 31523 75890 31629 47365 8095 35428 63780 9183 26790 60608 87793 17962 6198 11134 1033 85347
47792 53340 43258 10278 8807 6417 27300 66465 83500 18978 77389 20864 62407 3018 50101 10283 85260 81731 64000 3355
27159 44132 18890 53950 14741 23036 78264 20939 34170 79297 16286 88314 42637 59544 8592 57796 72313 42244 34261 65813
67574 28002 3029 39982 37372 53131 50265 32632 51214 30617 35988 78373 74750 61230 42323 5843 84266 36939 26782 34788

7
3rd-Semester-Fall-2022/PDS/Homework03/HW03_input2.txt Executable file
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@ -0,0 +1,7 @@
60
148 312 197 86 339 444 102 186 136 118
30 177 242 161 30 432 281 349 276 37
426 95 12 354 347 294 443 157 213 222
194 361 34 243 448 225 40 402 412 28
20 442 205 114 455 236 46 237 437 323
126 364 270 490 70 117 285 365 126 350

26
3rd-Semester-Fall-2022/PDS/Homework03/HW03_input3.txt Executable file
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@ -0,0 +1,26 @@
200
-2782 -25551 -8602 -15364 -12908 -23579 -25330 -22003
-2854 -1104 -12268 -1829 -4658 -26906 -24245 -29246
-24187 -25296 -5399 -2943 -2636 -825 -14677 -14568
-16981 -26283 -465 -23903 -8126 -15535 -180 -17260
-17438 -15135 -8977 -346 -15066 -10659 -22349 -17920
-11763 -10969 -26101 -22773 -14227 -20346 -22020 -14767
-15642 -27419 -17710 -24631 -4596 -2388 -9199 -21577
-28671 -9664 -21832 -6797 -1551 -28365 -409 -25341
-19852 -9386 -25687 -4918 -20045 -24388 -22838 -8160
-11709 -18939 -934 -25937 -15638 -29306 -10704 -7632
-3077 -4766 -2263 -7674 -7154 -11462 -5603 -5825
-27478 -27436 -18974 -5381 -2153 -19384 -722 -22005
-5122 -2761 -26923 -1520 -27149 -19761 -9680 -15211
-15052 -16966 -17500 -690 -16272 -4556 -8323 -19350
-9322 -16938 -3376 -16477 -28401 -8979 -22302 -2231
-12767 -17629 -7613 -14920 -13365 -8335 -6925 -24839
-11097 -3848 -26359 -14598 -29961 -12392 -29809 -21366
-29358 -23661 -28408 -21983 -28217 -6731 -17685 -13892
-22 -21061 -369 -4775 -40 -29023 -7006 -12808
-23004 -14619 -27728 -6369 -29307 -11006 -1209 -16756
-14854 -3920 -1354 -21168 -16312 -7516 -12534 -22023
-7529 -10942 -14006 -5747 -24026 -1691 -25991 -24048
-29104 -2712 -28823 -29144 -8087 -12181 -18304 -1092
-26801 -22385 -13813 -2460 -3391 -15022 -19216 -24597
-18943 -26922 -22117 -11607 -4438 -11003 -3630 -11968

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