14 lines
216 B
Verilog
Executable File
14 lines
216 B
Verilog
Executable File
module Lab1_testbench();
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reg [7:0] switch;
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wire [7:0] hex;
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Lab1 dut (hex, switch);
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initial
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switch <= 7'b0;
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always begin
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#10
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switch <= switch + 7'b0000001;
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end
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initial begin
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#1500 $stop;
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end
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endmodule |