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VLSI Lab 3 rev. 1

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Aidan Sharpe
2024-11-20 11:36:57 -05:00
parent b2f070c6d6
commit e97b5244ef
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7th-Semester-Fall-2024/VLSI/labs/lab-3/lab-3.aux Normal file
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\relax
\providecommand\hyper@newdestlabel[2]{}
\providecommand\HyperFirstAtBeginDocument{\AtBeginDocument}
\HyperFirstAtBeginDocument{\ifx\hyper@anchor\@undefined
\global\let\oldnewlabel\newlabel
\gdef\newlabel#1#2{\newlabelxx{#1}#2}
\gdef\newlabelxx#1#2#3#4#5#6{\oldnewlabel{#1}{{#2}{#3}}}
\AtEndDocument{\ifx\hyper@anchor\@undefined
\let\newlabel\oldnewlabel
\fi}
\fi}
\global\let\hyper@last\relax
\gdef\HyperFirstAtBeginDocument#1{#1}
\providecommand\HyField@AuxAddToFields[1]{}
\providecommand\HyField@AuxAddToCoFields[2]{}
\abx@aux@refcontext{nty/global//global/global}
\abx@aux@cite{0}{VLSICircuitsSystems}
\abx@aux@segm{0}{0}{VLSICircuitsSystems}
\abx@aux@cite{0}{VLSICircuitsSystems}
\abx@aux@segm{0}{0}{VLSICircuitsSystems}
\@writefile{toc}{\contentsline {section}{\numberline {I}Introduction}{2}{section.1}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {II}Inverter}{2}{section.2}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {1}{\ignorespaces The schematic for the inverter}}{2}{figure.1}\protected@file@percent }
\newlabel{fig:inv-sch}{{1}{2}{The schematic for the inverter}{figure.1}{}}
\newlabel{eqn:average-prop-delay}{{1}{2}{Inverter}{equation.2.1}{}}
\@writefile{lof}{\contentsline {figure}{\numberline {2}{\ignorespaces Simulated inverter input and output signals}}{2}{figure.2}\protected@file@percent }
\newlabel{fig:inverter-io}{{2}{2}{Simulated inverter input and output signals}{figure.2}{}}
\@writefile{lot}{\contentsline {table}{\numberline {I}{\ignorespaces Inverter Delay Characteristics}}{3}{table.1}\protected@file@percent }
\newlabel{tbl:inv-delay}{{I}{3}{Inverter Delay Characteristics}{table.1}{}}
\@writefile{lof}{\contentsline {figure}{\numberline {3}{\ignorespaces Inverter schematic symbol}}{3}{figure.3}\protected@file@percent }
\newlabel{fig:inv-symbol}{{3}{3}{Inverter schematic symbol}{figure.3}{}}
\@writefile{toc}{\contentsline {section}{\numberline {III}Conclusion}{3}{section.3}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {4}{\ignorespaces Inverter layout}}{3}{figure.4}\protected@file@percent }
\newlabel{fig:inv-layout}{{4}{3}{Inverter layout}{figure.4}{}}
\abx@aux@read@bbl@mdfivesum{66D8CCEED3AA0C3BA637E6C13B8A8AC2}
\abx@aux@defaultrefcontext{0}{VLSICircuitsSystems}{nty/global//global/global}
\gdef \@abspage@last{2}