VLSI Lab 3 rev. 1
This commit is contained in:
Aidan Sharpe
parent
b2f070c6d6
commit
e97b5244ef
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7th-Semester-Fall-2024/ECOMMS/final-project/sdr_stream.py
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7th-Semester-Fall-2024/ECOMMS/final-project/sdr_stream.py
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from rtlsdr import RtlSdr
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import numpy as np
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import matplotlib.pyplot as plt
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import scipy as sp
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import asyncio
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async def streaming():
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sdr = RtlSdr()
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async for samples in sdr.stream():
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await sdr.stop()
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sdr.close()
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7th-Semester-Fall-2024/ECOMMS/labs/lab2/AMModulation.slx
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7th-Semester-Fall-2024/ECOMMS/labs/lab2/AMModulation.slx
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7th-Semester-Fall-2024/ECOMMS/labs/lab2/am.py
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7th-Semester-Fall-2024/ECOMMS/labs/lab2/am.py
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import numpy as np
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import matplotlib.pyplot as plt
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import scipy as sp
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def lowpass(data, f_cutoff, f_s):
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nyq = 0.5*f_s
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normal_cutoff = f_cutoff/nyq
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b, a = sp.signal.butter(1, normal_cutoff, btype="low", analog=False)
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y = sp.signal.lfilter(b, a, data)
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return y
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def dsb_am(m, f_c, t):
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omega_c = 2*np.pi*f_c
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c = np.cos(omega_c*t)
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return 0.5*m*c + c
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def dsb_sc(m, f_c, t):
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omega_c = 2*np.pi*f_c
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c = np.cos(omega_c*t)
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return 0.5*m*c
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def product_demod(s, f_baseband, f_c, f_s, t):
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omega_c = 2*np.pi*f_c
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mixed = s*np.cos(omega_c*t)
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return lowpass(mixed, f_baseband, f_s)
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def main():
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T_s = 0.0005
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f_s = 1/T_s
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f_m = 10
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omega_m = 2*np.pi*f_m
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f_c = 100
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t = np.arange(0,1,T_s)
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f = np.linspace(0,f_s,len(t))
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m = np.sin(omega_m*t) + np.sin(omega_m/2*t)
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s_am = dsb_am(m, f_c, t)
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s_sc = dsb_sc(m, f_c, t)
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m_am_demod = product_demod(s_am, f_m, f_c, f_s, t)
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m_sc_demod = product_demod(s_sc, f_m, f_c, f_s, t)
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plt.plot(t, m, label="Original Message Signal")
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plt.plot(t, m_am_demod, label="Demodulated DSB-AM Signal")
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plt.plot(t, m_sc_demod, label="Demodulated DSB-SC Signal")
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plt.legend(loc="upper right")
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plt.show()
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if __name__ == "__main__":
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main()
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7th-Semester-Fall-2024/IoT-Hardware/assignments/Assignment5.docx
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7th-Semester-Fall-2024/VLSI/F24-ECE09.414-Syllabus_v2.pdf
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7th-Semester-Fall-2024/VLSI/labs/lab-3/border.tex
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7th-Semester-Fall-2024/VLSI/labs/lab-3/lab-3.aux
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7th-Semester-Fall-2024/VLSI/labs/lab-3/lab-3.bbl
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7th-Semester-Fall-2024/VLSI/labs/lab-3/lab-3.bcf
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||||
\documentclass[conference]{IEEEtran}
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\\\\\hline
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|
||||
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||||
\font\myfont=cmr12 at 15pt
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\title{\myfont Simple CMOS Gates}
|
||||
\author{Aidan Sharpe}
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\begin{document}
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\maketitle
|
||||
|
||||
\section{Introduction}
|
||||
In this lab, we designed and analyzed several simple CMOS gates. Specifically, we worked with an inverter, a transmission gate, and a two-input NAND gate. For each of the gates, a simple workflow was implemented. First, a schematic was created. This was done to create a simple, high-level model of the circuit. Next, the schematic was pulled into a simulation tool to determine delay characteristics. To enable rapid reusability of the design, a schematic symbol was then created. Finally, we designed a physical layout, and checked it to ensure proper spacing and that it matched the schematic.
|
||||
|
||||
\section{Inverter}
|
||||
The first, and simplest gate we created was a CMOS inverter. This device is made from one n-channel MOSFET (NMOS), and one p-channel MOSFET (PMOS). Its schematic is seen in figure \ref{fig:inv-sch}. Looking closely, the width of the NMOS is 120nm and the width of the PMOS is 240nm. This was done to match the resistances of the two devices.
|
||||
|
||||
The equivalent channel resistance of an NMOS is $R = \frac{R_0}{k}$, and for a PMOS, $R = \frac{2R_0}{k}$ \cite{VLSICircuitsSystems}. The constant $k$ is the ratio of the width of the MOSFET to the width of a unit transistor for that technology. For example, the unit transistor for 45nm is 120nm. Therefore, a PMOS will always have twice the resistance of an NMOS for the same width, and if the resistances are to match, then the PMOS must be twice as wide as the NMOS.
|
||||
|
||||
\begin{figure}[h]
|
||||
\center\includegraphics[width=0.4\textwidth]{graphics/inv-schematic.png}
|
||||
\caption{The schematic for the inverter}
|
||||
\label{fig:inv-sch}
|
||||
\end{figure}
|
||||
|
||||
With the schematic done, we then analyzed the delay characteristics of the inverter. Specifically, we looked at rise time $t_r$, fall time $t_f$, rising propagation delay $t_\text{pdr}$, falling propagation delay $t_\text{pdf}$, and average propagation delay $t_\text{pd}$. The rise time $t_r$ is simply the time it takes the output to rise from 20\% to 80\%, and the fall time $t_f$ is the time it takes for the output to fall from 80\% to 20\%. The rising propagation delay $t_\text{pdr}$ is the time between the input change reaching 50\% and a rising output change reaching 50\%. The rising propagation delay $t_\text{pdf}$ is the same but for a falling output change. The average propagation delay is simply the arithmetic mean of the rising and falling propagation delays:
|
||||
\begin{equation}
|
||||
t_\text{pd} = \frac{t_\text{pdr} + t_\text{pdf}}{2}
|
||||
\label{eqn:average-prop-delay}
|
||||
\end{equation}
|
||||
|
||||
For our inverter, we simulated a pulsed input with a period of 2[ns], seen as the green trace in figure \ref{fig:inverter-io}. Visually, the easiest delay to recognize is $t_\text{pdr}$ and $t_\text{pdf}$. They are simply the smallest difference between the green and red traces at 0.5[V]. Specifically, $t_\text{pdf}$ is the time between a green trace rising edge reaching 0.5[V] and its corresponding red trace falling edge reaching 0.5[V]. Likewise, $t_\text{pdr}$ is the time between a green trace falling edge reaching 0.5[V] and its corresponding red trace rising edge reaching 0.5[V].
|
||||
|
||||
\begin{figure}[h]
|
||||
\center\includegraphics[width=0.4\textwidth]{graphics/inverter-pins-io.png}
|
||||
\caption{Simulated inverter input and output signals}
|
||||
\label{fig:inverter-io}
|
||||
\end{figure}
|
||||
|
||||
Instead of eyeballing the time, we loaded the outputs of the simulation into a calculator tool to precisely calculate the time. This tool was used to calculate all five delay characteristics. The values of the delay characteristics are seen in table \ref{tbl:inv-delay}. It is important to note that the rise and fall times of the input signal are identical, but as seen in the table, the rise and fall times for the output are different. This effect is quite odd. The total output capacitance is $3C_0$ regardless of whether the output is rising or falling, and we picked our $k$ values such that the resistance was $R_0$ for both the pull-up and pull-down network. Therefore, regardless of the edge, the time constant should be $\tau = 3R_0C_0$. Regardless, we still have a difference between the rising and falling edges. The difference likely comes from an assumption we made. We assumed that the resistance for a PMOS is twice that of an NMOS of the same size, but this is merely an approximation to account for holes having lower mobility than electrons\cite{VLSICircuitsSystems}.
|
||||
|
||||
\begin{table}[H]
|
||||
\center
|
||||
\caption{Inverter Delay Characteristics}
|
||||
\begin{tabular}{c | c}
|
||||
$t_r$ & 12.33[ps]\\
|
||||
\hline
|
||||
$t_f$ & 11.98[ps]\\
|
||||
\hline
|
||||
$t_\text{pdr}$ & 22.69[ps]\\
|
||||
\hline
|
||||
$t_\text{pdf}$ & 21.45[ps]\\
|
||||
\hline
|
||||
$t_\text{pd}$ & 22.07[ps]\\
|
||||
\end{tabular}
|
||||
\label{tbl:inv-delay}
|
||||
\end{table}
|
||||
|
||||
With these characteristics in mind, we next created a symbol for the inverter. Without going into too much detail, the symbol allows the entire schematic and layout to be packaged into a repeatable block with a known visual indicator. The final symbol is seen in figure \ref{fig:inv-symbol}. In the future, we may place inverters just as we placed individual MOSFETs when creating the inverter schematic.
|
||||
|
||||
\begin{figure}[h]
|
||||
\center\includegraphics[width=0.4\textwidth]{graphics/inv-symbol.png}
|
||||
\caption{Inverter schematic symbol}
|
||||
\label{fig:inv-symbol}
|
||||
\end{figure}
|
||||
|
||||
Finally, we created the phyical layout for the inverter. The layout for the MOSFETs is premade with editable parameters. The layout was created with consideration for the width of and spacing between layout elements. Another important factor was the number of contacts between elements. For example, we used three contacts between the metal1 input and the polysilicon gate material to ensure a high quality and low resistance connection. We also used five contacts between ground and the p-substrate and between power and the n-well to maximize the contact area. Finally, we added pins to connect power, ground, input, and output nets to the design. The completed layout is seen in figure \ref{fig:inv-layout}.
|
||||
|
||||
\begin{figure}[h]
|
||||
\center\includegraphics[width=0.4\textwidth]{graphics/inv-layout.png}
|
||||
\caption{Inverter layout}
|
||||
\label{fig:inv-layout}
|
||||
\end{figure}
|
||||
|
||||
To ensure that our layout met the design rules imposed by the technology library, we used a design rule checker. Our initial design had some small errors, such as the n-well being too close to the contacts to power, but the design rule checker enabled us to rapidly resolve these issues. We also ran another check to ensure that the connections in the layout matched the connections in the schematic. After adding the proper pins, this check also passed. With both checks completed, our inverter was finished.
|
||||
|
||||
\section{Conclusion}
|
||||
The workflow implemented enables the rapid re-use of circuits. This concept is important as it is not feasible to layout every MOSFET and every connection in a larger design. By building up a design from previously designed components, keeping track of the characteristics of each piece along the way, it is much easier to create complex digital circuits.
|
||||
|
||||
This process is the essence of VLSI. It is not possible for people to build a CPU with billions of transistors one MOSFET at a time. Very large scale designs are only made possible by slowly building up a subsystem by using repeatable elements, and abstracting away the fine details.
|
||||
|
||||
\printbibliography
|
||||
\end{document}
|
||||
19
7th-Semester-Fall-2024/VLSI/labs/lab-3/references.bib
Normal file
19
7th-Semester-Fall-2024/VLSI/labs/lab-3/references.bib
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@ -0,0 +1,19 @@
|
||||
@online{VLSISystemDesign,
|
||||
title = {Noise Margin},
|
||||
year = 2017,
|
||||
url = {https://www.vlsisystemdesign.com/noise-margin/}
|
||||
}
|
||||
|
||||
@online{VddNaming,
|
||||
title = {What is the difference between VCC, VDD, VEE, VSS},
|
||||
author = {Olin Lathrop},
|
||||
year = 2011,
|
||||
url = {https://electronics.stackexchange.com/questions/17382/what-is-the-difference-between-v-cc-v-dd-v-ee-v-ss}
|
||||
}
|
||||
|
||||
@book{VLSICircuitsSystems,
|
||||
title = {CMOS VLSI Design a Circuits and Systems Perspective, Fourth Edition},
|
||||
year = 2011,
|
||||
author = {Neil H. E. Weste, David Money Harris},
|
||||
publisher = {Pearson}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user