Rowan-Classes/7th-Semester-Fall-2024/VLSI/labs/lab-1-2/lab-1-2.tex

\documentclass[conference]{IEEEtran}
\usepackage[siunitx]{circuitikz}
\usepackage{graphicx}
%\usepackage{lipsum}
\usepackage{color}
\usepackage{enumitem}
\usepackage{epsfig} 
\usepackage{mathptmx} 
\usepackage{times} 
\usepackage{amsmath}
\usepackage{amssymb}  
\usepackage{float}
\usepackage{hyperref}
%\usepackage{setspace}
%\usepackage{tikz}
\usepackage{circuitikz}
\usepackage{pgfplots}
\usepackage{textcomp}
%\usepgfplotslibrary{external}
%\tikzexternalize
%\usepackage[utf8]{inputenc}
%\usepackage[english]{babel}
%\usepackage{pgf}
\usepackage{pgfpages}
\usepackage[margin=0.4in]{geometry}
\usepackage{lmodern}
\usepackage{datetime}
\usepackage{ragged2e}
\input{border.tex}
\pgfpagesuselayout{boxed}

\hyphenation{op-tical net-works semi-conduc-tor}% correct bad hyphenation here

\font\myfont=cmr12 at 15pt 
\title{\myfont VLSI Labs 1\&2 \\ Simple MOSFET \& CMOS Inverter Trends}
\author{Aidan Sharpe}

\providecommand{\keywords}[1]{\textbf{\textit{Keywords---}} #1}
\providecommand{\e}[1]{\ensuremath{\times 10^{#1}}}
\setlength{\columnsep}{7mm}
\pgfplotsset{compat=1.15}
\begin{document}
\maketitle

\section{Introduction}
While they are commonly treated as three-terminal devices in introductory electronics classes, MOSFETs are actually four-terminal devices. In discrete, three-terminal designs, the body pin and the source pin are tied together internally. In CMOS VLSI desin, all four pins play an important role. Having a discrete body pin provides each transistor with its own power or ground reference depending on the type of MOSFET. 

In CMOS VLSI design, there are two types of complementary MOSFETs, hence the name CMOS. The two types are the n-channel MOSFET (NMOS) and the p-channel MOSFET (PMOS). N-channel MOSFETs behave like a switch that is normally open, while p-channel MOSFETs behave like a normally closed switch. To change the state of the switch, a voltage $V_{gs}$ is applied to the gate pin.

We will discuss the exact behavior of the two types of MOSFETs further throughout the following two sections. In the final section, we will explore and discuss the properies and behaviors of a CMOS inverter.

\section{NMOS Characteristics}
The Shockley first-order model is a good approximation of the relationship between the input voltages and the current through a MOSFET. The model approximates the current trhough an NMOS $I_{ds}$ is
\begin{equation}
	I_{ds} = \begin{cases}
		0 & V_{gs} < V_t \\
		\beta \left(V_{gs} - V_t - \frac{V_{ds}}{2}\right) V_{ds} & V_{ds} < V_{dsat} \\
		\frac{\beta}{2}\left(V_{gs} - V_t\right)^2 & V_{ds} > V_{dsat}
	\end{cases}
	\label{eqn:nmos-shockley-first-order}
\end{equation}
where $V_{gs}$ is the voltage between the gate and source, $V_t$ is the threshold voltage, $V_{ds}$ is the voltage between the drain and the source, $V_{dsat} = V_{gs} - V_t$, and $\beta$ is a constant based on the physical properties of the MOSFET. 

We parametrically varied $V_{gs}$ and $V_{ds}$ using a Python. Then, we plotted $I_{ds}$ using the model described in equation \ref{eqn:nmos-shockley-first-order}. Seen in figure \ref{fig:nmos-shockley-first-order}, increasing $V_{gs}$ will increase the current. Furthermore, increasing $V_{ds}$ will also increase the current, but only up to a point. After reaching that point, the current does not change with $V_{ds}$.

\begin{figure}[H]
	\center\includegraphics[width=0.4\textwidth]{graphics/simulated-iv-curves.png}
	\caption{Plot of Shockley first order model for an n-channel MOSFET}
	\label{fig:nmos-shockley-first-order}
\end{figure}

We then used a simulation tool that takes into account the non-ideal effects of MOSFETs to provide a more accurate plot of the relationship between input voltages and current. First, an NMOS was placed in the schematic, along with some voltage sources with variable volages. It is important that the voltages be variable, so a parametric test may be run. The final schematic is seen in figure \ref{fig:nmos-iv-schematic}.

\begin{figure}[H]
	\center\includegraphics[width=0.4\textwidth]{graphics/nmos-iv-schematic.png}
	\caption{NMOS parametric test schematic}
	\label{fig:nmos-iv-schematic}
\end{figure}

\section{The Noise Margin}
The noise margin is the amount of noise that a CMOS circuit can withstand without compromising the operation of the circuit\cite{VLSI_System_Design}. This region is necessary to create a buffer that prevents small amounts of noise from switching the logic. There are two noise margins: noise margin high (NM\textsubscript{H}) and noise margin low (NM\textsubscript{L}). 

The two noise margins are defined in terms of four key voltages on the voltage transfer curve (VTC) seen in figure \ref{fig:inv_vtc}: $V_\text{IL}$, $V_\text{IH}$, $V_\text{OL}$, and $V_\text{OH}$. $V_\text{IL}$ is defined as the lower input voltage where the slope of the VTC is -1, and $V_\text{IH}$ is defined as the upper input voltage meeting the same requirement. $V_\text{OL}$ is defined as the output voltage when the input voltage is equal to $V_\text{IH}$, and similarly, $V_\text{OH}$ is defined as the output voltage when the input voltage is equal to $V_\text{IL}$.

\begin{figure}[H]
	\center
	\includegraphics[width=0.4\textwidth]{graphics/inverter-noise-margin.png}
	\caption{The VTC and its derivative for a CMOS inverter with $w_p=240$[nm] and $w_n=120$[nm]}
	\label{fig:inv_vtc}.
\end{figure}

\begin{table}[H]
\center
\caption{Important VTC voltages}
\begin{tabular}{c | c}
	$V_\text{IL}$ & 2.357 \\
	\hline
	$V_\text{IH}$ & 3.531 \\
	\hline
	$V_\text{OL}$ & 0.683 \\
	\hline
	$V_\text{OH}$ & 4.118 \\
\end{tabular}
\end{table}

With these voltages now defined, the noise margin high was calculated using
\begin{equation}
	\text{NM}_\text{H} = V_\text{OH} - V_\text{IH},
\end{equation}
and noise margin low was calculated with
\begin{equation}
	\text{NM}_\text{L} = V_\text{IL} - V_\text{OL}.
\end{equation}

\section{Discussion}

\section{Conclusion}

\end{document}