361 lines
5.5 KiB
C
Executable File
361 lines
5.5 KiB
C
Executable File
//******************************************************************************
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// MSP430FR235x Demo - SAC-L3, DAC Buffer Mode
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//
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// Description: Configure SAC-L3 for DAC Buffer Mode. Use the 12 bit DAC to
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// output positive ramp. The OA is set in buffer mode to improve DAC output
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// drive strength. Internal 2.5V reference is selected as DAC reference.
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// Observe the output of OA0O pin with oscilloscope.
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// ACLK = n/a, MCLK = SMCLK = default DCODIV ~1MHz.
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//
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// MSP430FR235x
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// -------------------
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// /|\| |
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// | | |
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// --|RST DAC12->OA0O|--> oscilloscope
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//
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// Darren Lu
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// Texas Instruments Inc.
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// Oct. 2016
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// Built with IAR Embedded Workbench v6.50 & Code Composer Studio v6.2
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//******************************************************************************
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#include <msp430.h>
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void gpioInit();
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void adcInit();
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void sacInit();
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void timerInit();
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unsigned int DAC_data=0;
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unsigned int ADC_Result = 0;
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int main(void)
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{
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WDTCTL = WDTPW + WDTHOLD; // Stop watch dog timer
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gpioInit();
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PM5CTL0 &= ~LOCKLPM5; // Disable the GPIO power-on default high-impedance mode
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// to activate previously configured port settings
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sacInit();
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timerInit();
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adcInit();
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while(1){
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ADCCTL0 |= ADCENC | ADCSC; // Sampling and conversion start
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__bis_SR_register(LPM0_bits | GIE); // LPM0, ADC_ISR will force exit
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__no_operation(); // For debug only
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DAC_data = ADC_Result;
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__delay_cycles(10);
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}
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}
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void gpioInit()
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{
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P1OUT &= ~BIT0; // Clear P1.0 output latch for a defined power-on state
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P1DIR |= BIT0; // Set P1.0 to output direction
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P1SEL0 |= BIT1; // Select P1.1 as OA0O function
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P1SEL1 |= BIT1; // OA is used as buffer for DAC
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// Configure ADC A5 pin
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P1SEL0 |= BIT5;
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P1SEL1 |= BIT5;
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}
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void sacInit()
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{
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// Configure reference module
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PMMCTL0_H = PMMPW_H; // Unlock the PMM registers
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PMMCTL2 = INTREFEN | REFVSEL_2; // Enable internal 2.5V reference
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while(!(PMMCTL2 & REFGENRDY)); // Poll till internal reference settles
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SAC0DAC = DACSREF_1 + DACLSEL_2 + DACIE; // Select int Vref as DAC reference
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SAC0DAT = DAC_data; // Initial DAC data
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SAC0DAC |= DACEN; // Enable DAC
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SAC0OA = NMUXEN + PMUXEN + PSEL_1 + NSEL_1;//Select positive and negative pin input
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SAC0OA |= OAPM_0; // Select low speed and low power mode
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SAC0PGA = MSEL_1; // Set OA as buffer mode
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SAC0OA |= SACEN + OAEN; // Enable SAC and OA
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}
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void timerInit()
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{
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// Use TB2.1 as DAC hardware trigger
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TB2CCR0 = 100-1; // PWM Period/2
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TB2CCTL1 = OUTMOD_6; // TBCCR1 toggle/set
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TB2CCR1 = 50; // TBCCR1 PWM duty cycle
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TB2CTL = TBSSEL__SMCLK | MC_1 | TBCLR; // SMCLK, up mode, clear TBR
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}
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void adcInit()
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{
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// Configure ADC12
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ADCCTL0 |= ADCSHT_2 | ADCON; // ADCON, S&H=16 ADC clks
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ADCCTL1 |= ADCSHP; // ADCCLK = MODOSC; sampling timer
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ADCCTL2 &= ~ADCRES; // clear ADCRES in ADCCTL
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ADCCTL2 |= ADCRES_2; // 12-bit conversion results
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ADCMCTL0 |= ADCINCH_5; // A5 ADC input select; Vref=AVCC
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ADCIE |= ADCIE0; // Enable ADC conv complete interrupt
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}
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#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
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#pragma vector = SAC0_SAC2_VECTOR
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__interrupt void SAC0_ISR(void)
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#elif defined(__GNUC__)
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void __attribute__ ((interrupt(SAC0_SAC2_VECTOR))) SAC0_ISR (void)
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#else
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#error Compiler not supported!
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#endif
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{
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switch(__even_in_range(SAC0IV,SACIV_4))
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{
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case SACIV_0: break;
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case SACIV_2: break;
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case SACIV_4:
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//DAC_data++;
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DAC_data &= 0xFFF;
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SAC0DAT = DAC_data; // DAC12 output positive ramp
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break;
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default: break;
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}
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}
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// ADC interrupt service routine
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#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
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#pragma vector=ADC_VECTOR
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__interrupt void ADC_ISR(void)
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#elif defined(__GNUC__)
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void __attribute__ ((interrupt(ADC_VECTOR))) ADC_ISR (void)
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#else
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#error Compiler not supported!
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#endif
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{
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switch(__even_in_range(ADCIV,ADCIV_ADCIFG))
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{
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case ADCIV_NONE:
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break;
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case ADCIV_ADCOVIFG:
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break;
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case ADCIV_ADCTOVIFG:
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break;
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case ADCIV_ADCHIIFG:
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break;
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case ADCIV_ADCLOIFG:
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break;
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case ADCIV_ADCINIFG:
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break;
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case ADCIV_ADCIFG:
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ADC_Result = ADCMEM0;
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P1OUT ^= BIT0;
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__bic_SR_register_on_exit(LPM0_bits); // Clear CPUOFF bit from LPM0
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break;
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default:
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break;
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}
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} |