\documentclass[conference]{IEEEtran} \usepackage[siunitx]{circuitikz} \usepackage{graphicx} %\usepackage{lipsum} \usepackage{color} \usepackage{enumitem} \usepackage{epsfig} \usepackage{mathptmx} \usepackage{times} \usepackage{amsmath} \usepackage{amssymb} \usepackage{float} \usepackage{hyperref} %\usepackage{setspace} %\usepackage{tikz} \usepackage{circuitikz} \usepackage{pgfplots} \usepackage{textcomp} %\usepgfplotslibrary{external} %\tikzexternalize %\usepackage[utf8]{inputenc} %\usepackage[english]{babel} %\usepackage{pgf} \usepackage{pgfpages} \usepackage[margin=0.4in]{geometry} \usepackage{lmodern} \usepackage{datetime} \usepackage{ragged2e} \input{border.tex} \pgfpagesuselayout{boxed} \hyphenation{op-tical net-works semi-conduc-tor}% correct bad hyphenation here \font\myfont=cmr12 at 15pt \title{\myfont VLSI Labs 1\&2 \\ Simple MOSFET \& CMOS Inverter Trends} \author{Aidan Sharpe} \providecommand{\keywords}[1]{\textbf{\textit{Keywords---}} #1} \providecommand{\e}[1]{\ensuremath{\times 10^{#1}}} \setlength{\columnsep}{7mm} \pgfplotsset{compat=1.15} \begin{document} \maketitle \section{Introduction} \section{Modelling a MOSFET} \section{The Noise Margin} The noise margin is the amount of noise that a CMOS circuit can withstand without compromising the operation of the circuit\cite{VLSI_System_Design}. This region is necessary to create a buffer that prevents small amounts of noise from switching the logic. There are two noise margins: noise margin high (NM\textsubscript{H}) and noise margin low (NM\textsubscript{L}). The two noise margins are defined in terms of four key voltages on the voltage transfer curve (VTC) seen in figure \ref{fig:inv_vtc}: $V_\text{IL}$, $V_\text{IH}$, $V_\text{OL}$, and $V_\text{OH}$. $V_\text{IL}$ is defined as the lower input voltage where the slope of the VTC is -1, and $V_\text{IH}$ is defined as the upper input voltage meeting the same requirement. $V_\text{OL}$ is defined as the output voltage when the input voltage is equal to $V_\text{IH}$, and similarly, $V_\text{OH}$ is defined as the output voltage when the input voltage is equal to $V_\text{IL}$. \begin{figure}[H] \center \includegraphics[width=0.4\textwidth]{graphics/inverter-noise-margin.png} \caption{The VTC and its derivative for a CMOS inverter with $w_p=240$[nm] and $w_n=120$[nm]} \label{fig:inv_vtc}. \end{figure} \begin{table}[H] \center \caption{Important VTC voltages} \begin{tabular}{c | c} $V_\text{IL}$ & 2.357 \\ \hline $V_\text{IH}$ & 3.531 \\ \hline $V_\text{OL}$ & 0.683 \\ \hline $V_\text{OH}$ & 4.118 \\ \end{tabular} \end{table} With these voltages now defined, the noise margin high was calculated using \begin{equation} \text{NM}_\text{H} = V_\text{OH} - V_\text{IH}, \end{equation} and noise margin low was calculated with \begin{equation} \text{NM}_\text{L} = V_\text{IL} - V_\text{OL}. \end{equation} \section{Discussion} \section{Conclusion} \end{document}