\documentclass{report}

\input{preamble}
\input{macros}
\input{letterfonts}

\title{\Huge{CMOS VLSI Design}}
\author{\huge{Aidan Sharpe}}
\date{}

\begin{document}

\maketitle
\newpage% or \cleardoublepage
% \pdfbookmark[<level>]{<title>}{<dest>}
\pdfbookmark[section]{\contentsname}{toc}
\tableofcontents
\pagebreak

\chapter{CMOS Circuits, Fabrication, and Layout Design Rules}
\section{A Brief History}
First transistor developed at Bell Labs in 1947. 

\section{MOSFET Overview}
MOSFETs are four-pin devices (source, gate, drain, body). The gate and body are conductors, while the source and drain are semiconductors. For nMOS devices, the body pin should always be tied to the lowest potential. For a pMOS device, the body pin is tied to the highest potential.

\nt{For CMOS circuits, the output power always comes from the rails, not the gate.}

\subsection{Power Supply Voltage}
\begin{itemize}
	\item GND = 0V
	\item In 1980's $V_{DD}$ = 5V
	\item $V_{DD}$ has decreased over time
	\item 3.3V and 1.2V CMOS circuits are common today
\end{itemize}

\section{CMOS Transistor Theory}
A transistor that is on passes a finite amount of current dependent on terminal voltages. The gate, source, and drain all have capacitance. Capacitance and current determines the speed and timing of these devices.
\begin{equation}
	I = C \frac{dv}{dt}
\end{equation}

\begin{figure}
	\center
	\includegraphics[width=0.5\textwidth]{nmos-dimensions.png}
	\caption{nMOS dimensions}
	\label{fig:nmos-dimensions}
\end{figure}

MOSFETs have operation modes: accumulation, depletion, and inversion. These modes depend on the voltages $V_g$, $V_d$, and $V_s$. Source and drain are symmetric diffusion terminals, but by convention, the source is the terminal at lower voltage; hence, $V_{ds} \ge 0$. The body of an nMOS should be grounded, and, at this point, it is safe to assume that the source terminal is also grounded.

MOSFETs also have regions of operation: cutoff, linear, and saturation. During cutoff, $I_{ds} \approx 0$. During the linear region, $I_{ds} \propto V_{gs}$, and during the saturation regions, increasing voltage no longer increases current.

\begin{equation}
	Q_\text{channel} = CV
\end{equation}

\begin{equation}
	C = C_g = \veps_\text{oxide} \frac{WL}{t_\text{oxide}} = C_\text{oxide} WL
\end{equation}

\begin{equation}
	C_\text{oxide} = \frac{\veps_\text{oxide}}{t_\text{oxide}}
\end{equation}

Electrons are propelled by the lateral electric field between source and drain $E = V_{ds} / L$.

If $V_{gd} < V_t$, the channel pinches off near the drain, meaning that an increase in voltage does not cause an increase in current.

\begin{equation}
	I_{ds} = \begin{cases}
		0 & V_{gs} < V_t \\
		\beta\lt(V_{gs} - V_t - \frac{V_{ds}}{2}\rt)V_{ds} & V_{ds} < V_\text{saturation} \\
		\frac{\beta}{2}\lt(V_{gs} - V_{t}\rt)^2 & V_{ds} > V_\text{saturation} 
	\end{cases}
\end{equation}

Since pMOS transistors pass power rather than creating a ground connection, they must be larger than nMOS transistors. For the case of this class: $\mu_p = 2\mu_n$.

\section{Capacitance}
The gate capacitance per micron is typically about 2fF.

\section{Logical Gate Truth Tables}
\begin{table}[!h]
	\caption{Truth table of a NOT gate}
	%\label{tbl:truth-not}
	\begin{center}
	\begin{tabular}{c | c}
		in & out \\
		\hline
		1 & 0 \\
		0 & 1 \\
	\end{tabular}
\end{center}
\end{table}
\begin{table}[!h]
	\caption{Truth table of a NAND gate}
	\begin{center}
	\begin{tabular}{c c | c}
		A & B & Y \\
		\hline
		0 & 0 & 1 \\
		0 & 1 & 1 \\
		1 & 0 & 1 \\
		1 & 1 & 0 \\
	\end{tabular}
\end{center}
\end{table}

With the goal to set the correct output to $V_{DD}$ and GND, shorts must be avoided.
Simple guides:
\begin{enumerate}
	\item nMOS can only pass "0"
	\item pMOS can only pass "1"
	\item Always use pMOS in a pull-up network and nMOS in a pull-down network, with the output between them
	\item Only one of the two networks should be on at any given time
\end{enumerate}

\subsection{Implementing Arbitrary Functions}
Realize the pull-down network by inspection (looking at the truth table), and then use deMorgan's theorem to manipulate.
\ex{}
{
	Given the function $F = \overline{A + BC}$, the pull-down network implements $A$ OR $B$ AND $C$. Keep in mind that MOSFETs in series have the effect of AND, and MOSFETs in parallel have the effect of OR. Next, use deMorgan's theorem to implement $\overline{A + BC}$ as a non-inverted function. This becomes $\bar{A} \cdot (\bar{B} + \bar{C})$. Finally, combine the pull-up and pull down networks.
}

\section{Nonideal Transistor Theory}
\end{document}
