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\font\myfont=cmr12 at 15pt 
\title{\myfont Applying Simple CMOS Gates} 
\author{Aidan Sharpe}

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\maketitle

\section{Introduction}
The humble adder is arguably the most important of all arithmetic devices found in a computer. Both subtractors and multipliers may be built using very little extra circuitry, since subtraction is the same as adding a negative, and multiplication is just repeated addition.

The simplest adding circuit is the half adder. It has two inputs, $A$ and $B$, and two outputs, sum and carry. The sum output will be high if only one of the two inputs is high, and the carry output will be high if both inputs are high. More complex devices can be built upon this simple framework.

\section{Background}
The full adder is a device with three inputs---$A$, $B$ and carry in ($C_\text{in}$)---and two outputs---sum ($S$) and carry out ($C_\text{out}$). The sum bit will be high when the sum of $A$, $B$, and $C_\text{in}$ modulo two is one. $C_\text{out}$ will be high when the sum of $A$, $B$, and $C_
\text{in}$ is greater than one. This relationship is seen for all combinations of $A$, $B$, and $C_\text{in}$ in table \ref{tbl:full-adder-truth}.

\begin{table}[h]
	\center
	\caption{Full Adder Truth Table}
	\begin{tabular}{ c c c | c c}
		$A$ & $B$ & $C_\text{in}$ & $S$ & $C_\text{out}$\\
		\hline
		0 & 0 & 0 & 0 & 0 \\
		0 & 0 & 1 & 1 & 0 \\
		0 & 1 & 0 & 1 & 0 \\
		0 & 1 & 1 & 0 & 1 \\
		1 & 0 & 0 & 1 & 0 \\
		1 & 0 & 1 & 0 & 1 \\
		1 & 1 & 0 & 0 & 1 \\
		1 & 1 & 1 & 1 & 1 \\
	\end{tabular}
	\label{tbl:full-adder-truth}
\end{table}

Typically, the full adder is thought of as two half adders with their carry outs ``or-ed" together. The sum output of the half adder has the same truth table as an XOR gate, and the carry output has the same truth table as an AND gate. Therefore, a half adder can be modeled as an XOR gate and an AND gate. This simple representation of the full adder is seen in figure \ref{fig:simple-full-adder}. 

\begin{figure}[h]
	\center\includegraphics[width=\linewidth]{graphics/simple-full-adder.png}
	\caption{Simple full adder schematic}
	\label{fig:simple-full-adder}.
\end{figure}

The function of each gate in figure \ref{fig:simple-full-adder} makes the overall operation clear. When designing circuits in logic simulators, this topology is common. For example, figure \ref{fig:simple-full-adder} was constructed using Logisim, and the same topology is also used in many computers built in the hit sandbox game Minecraft.

\section{Schematic Design}
Previously, we designed a half adder schematic, seen in figure \ref{fig:half-adder-schematic}, containing four NAND gates. We purposefully left the carry out inverted, so building the full adder would be easier.

\begin{figure}[h]
	\center\includegraphics[width=\linewidth]{graphics/half-adder-schematic.png}
	\caption{Half adder schematic}
	\label{fig:half-adder-schematic}
\end{figure}

Recall the full adder design from figure \ref{fig:simple-full-adder}. We originally ``or-ed" together the carry output from each of the two half adders. With our CMOS design, however, we cannot simply build AND gates and OR gates, as CMOS is restricted to inverting functions. By De Morgan's laws, however, we know that $A+B$ is the same as $\overline{\bar{A}\bar{B}}$. With our half adder design, getting an inverted carry out is easier than getting a non-inverted carry out. Therefore, we can just add another NAND gate to have the same effect as ``or-ing" the two non-inverted carry outs. This additional NAND gate is seen in our final schematic for the full adder seen in figure \ref{fig:full-adder-schematic}.

\begin{figure}[h]
	\center\includegraphics[width=\linewidth]{graphics/full-adder-schematic.png}
	\caption{Full adder schematic}
	\label{fig:full-adder-schematic}
\end{figure}

This final design for the full adder is made from nine NAND gates total---four from each half adder and one for the carry out. With our final design, the last step was to size the gates using logical effort calculations to minimize delay. 

\section{Logical Effort Calculations}
There are two ways of calculating the logical effort for the full adder. One way would be to consider the two half adders as gates and to size them as a whole. The other way, the method we opted to choose, was to size all nine individual NAND gates. 

The smallest size for a NAND gate has all n-channel MOSFETs and all p-channel MOSFETs at a width of $w=2\lambda$.

\section{Conclusion}

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