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\font\myfont=cmr12 at 15pt 
\title{\myfont Simple CMOS Gates} 
\author{Aidan Sharpe}

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\section{Introduction}
In this lab, we designed and analyzed several simple CMOS gates. Specifically, we worked with an inverter, a transmission gate, and a two-input NAND gate. For each of the gates, a simple workflow was implemented. First, a schematic was created. This was done to create a simple, high-level model of the circuit. Next, the schematic was pulled into a simulation tool to determine delay characteristics. To enable rapid reusability of the design, a schematic symbol was then created. Finally, we designed a physical layout, and checked it to ensure proper spacing and that it matched the schematic.

\section{Inverter}
The first, and simplest gate we created was a CMOS inverter. This device is made from one n-channel MOSFET (NMOS), and one p-channel MOSFET (PMOS). Its schematic is seen in figure \ref{fig:inv-sch}. Looking closely, the width of the NMOS is 120nm and the width of the PMOS is 240nm. This was done to match the resistances of the two devices. 

The equivalent channel resistance of an NMOS is $R_n = \frac{R}{k}$, and for a PMOS, $R_p = \frac{2R}{k}$ \cite{VLSICircuitsSystems}. The constant $k$ is the ratio of the width of the MOSFET to the width of a unit transistor for that technology. For example, the unit transistor for our 45[nm] design library is 120[nm]. Therefore, a PMOS will always have twice the resistance of an NMOS of the same width, and if the resistances are to match, then the PMOS must be twice as wide as the NMOS.

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/inv-schematic.png}
	\caption{The schematic for the inverter}
	\label{fig:inv-sch}
\end{figure}

With the schematic done, we then analyzed the delay characteristics of the inverter. Specifically, we looked at rise time $t_r$, fall time $t_f$, rising propagation delay $t_\text{pdr}$, falling propagation delay $t_\text{pdf}$, and average propagation delay $t_\text{pd}$. The rise time $t_r$ is simply the time it takes the output to rise from 20\% to 80\%, and the fall time $t_f$ is the time it takes for the output to fall from 80\% to 20\%. The rising propagation delay $t_\text{pdr}$ is the time between the input change reaching 50\% and a rising output change reaching 50\%. The rising propagation delay $t_\text{pdf}$ is the same but for a falling output change. The average propagation delay is simply the arithmetic mean of the rising and falling propagation delays:
\begin{equation}
	t_\text{pd} = \frac{t_\text{pdr} + t_\text{pdf}}{2}
	\label{eqn:average-prop-delay}
\end{equation}

For our inverter, we simulated a pulsed input with a period of 2[ns], seen as the green trace in figure \ref{fig:inverter-io}. Visually, the easiest delay to recognize is $t_\text{pdr}$ and $t_\text{pdf}$. They are simply the smallest difference between the green and red traces at 0.5[V]. Specifically, $t_\text{pdf}$ is the time between a green trace rising edge reaching 0.5[V] and its corresponding red trace falling edge reaching 0.5[V]. Likewise, $t_\text{pdr}$ is the time between a green trace falling edge reaching 0.5[V] and its corresponding red trace rising edge reaching 0.5[V]. 

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/inverter-pins-io.png}
	\caption{Simulated inverter input and output signals}
	\label{fig:inverter-io}
\end{figure}

Instead of eyeballing the time, we loaded the outputs of the simulation into a calculator tool to precisely calculate the time. This tool was used to calculate all five delay characteristics. The values of the delay characteristics are seen in table \ref{tbl:inv-delay}. It is important to note that the rise and fall times of the input signal are identical, but as seen in the table, the rise and fall times for the output are different. This effect is quite odd. The total output capacitance is $3C$ regardless of whether the output is rising or falling, and we picked our $k$ values such that the resistance was $R$ for both the pull-up and pull-down network. Therefore, regardless of the edge, the time constant should be $\tau = 3RC$. Regardless, we still have a difference between the rising and falling edges. The difference likely comes from an assumption we made. We assumed that the resistance for a PMOS is twice that of an NMOS of the same size, but this is merely an approximation to account for holes having lower mobility than electrons\cite{VLSICircuitsSystems}.

\begin{table}[H]
\center
\caption{Inverter Delay Characteristics}
\begin{tabular}{c | c}
	$t_r$ & 12.33[ps]\\
	\hline
	$t_f$ & 11.98[ps]\\
	\hline
	$t_\text{pdr}$ & 22.69[ps]\\
	\hline
	$t_\text{pdf}$ & 21.45[ps]\\
	\hline
	$t_\text{pd}$ & 22.07[ps]\\
\end{tabular}
\label{tbl:inv-delay}
\end{table}

With these characteristics in mind, we next created a symbol for the inverter. Without going into too much detail, the symbol allows the entire schematic and layout to be packaged into a repeatable block with a known visual indicator. The final symbol is seen in figure \ref{fig:inv-symbol}. In the future, we may place inverters just as we placed individual MOSFETs when creating the inverter schematic.

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/inv-symbol.png}
	\caption{Inverter schematic symbol}
	\label{fig:inv-symbol}
\end{figure}

Finally, we created the phyical layout for the inverter. The layout for the MOSFETs is premade with editable parameters. The layout was created with consideration for the width of and spacing between layout elements. Another important factor was the number of contacts between elements. For example, we used three contacts between the metal1 input and the polysilicon gate material to ensure a high quality and low resistance connection. We also used five contacts between ground and the p-substrate and between power and the n-well to maximize the contact area. Finally, we added pins to connect power, ground, input, and output nets to the design. The completed layout is seen in figure \ref{fig:inv-layout}.

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/inv-layout.png}
	\caption{Inverter layout}
	\label{fig:inv-layout}
\end{figure}

To ensure that our layout met the design rules imposed by the technology library, we used a design rule checker. Our initial design had some small errors, such as the n-well being too close to the contacts to power, but the design rule checker enabled us to rapidly resolve these issues. We also ran another check to ensure that the connections in the layout matched the connections in the schematic. After adding the proper pins, this check also passed. With both checks completed, our inverter was finished.

\section{Transmission Gate}
A transmission gate is similar in construction to an inverter, consisting of one NMOS and one PMOS. A schematic for a CMOS transmission gate is seen in figure \ref{fig:trans-schematic}. When $C$ is low ($\sim C$ is high), the output $Y$ is the same as the input $A$, and when $C$ is high ($\sim C$ is low), the output $Y$ is floating. The transmission gate works well in this layout because the PMOS passes a "strong one" and the NMOS passes a "strong zero". 
\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/tran-schematic.png}
	\caption{Transmission gate schematic}
	\label{fig:trans-schematic}
\end{figure}

With only one transmission gate, the output signal quality is very good. One thing to keep in mind, however, is that unlike an inverter, where the output power comes from the rails, with a transmission gate, the output power comes directly from the input. Therefore, any noise present in the input will get passed to the output. With a standard CMOS gate, the output noise does not build from stage to stage.

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/tran-signals.png}
	\caption{Transmission gate timing diagram}
	\label{fig:trans-signals}
\end{figure}

When it comes to the pysical layout of the transmission gate shown in figure \ref{fig:trans-layout}, one thing to keep in mind is that $C$ and $\sim C$ are inaccessible on metal1. Therefore, an additional via---metal1 to metal2---would be required for each of the two control inputs.

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/tran-layout.png}
	\caption{Transmission gate layout}
	\label{fig:trans-layout}
\end{figure}


\section{NAND Gate}
The NAND gate is the fastest two input CMOS logic gate. It has an input capacitance of 4C compared to the 5C of a NOR gate. The truth table for a NAND is seen in table \ref{tbl:nand-truth}. The output is low only when all inputs are high.

\begin{table}[h]
	\center
	\caption{NAND gate truth table}
	\begin{tabular}{c c | c}
		A & B & X\\
		\hline
		0 & 0 & 1\\
		0 & 1 & 1\\
		1 & 0 & 1\\
		1 & 1 & 0\\
	\end{tabular}
	\label{tbl:nand-truth}
\end{table}

The simplest two-input CMOS NAND gate has a pull-up network with two PMOS's in series and a pull-down network with two NMOS's in parallel, seen in figure \ref{fig:nand-schematic}. To establish the same resistance in both networks, all gates are twice the size of a unit transistor. Since the input capacitance is the sum of all gate capacitances for a given input, and the gate capacitance for both n-channel and p-channel MOSFETs is $kC$, we have a total input capacitance of $2C + 2C = 4C$. 

For our 45[nm] technology package, the unit transistor is 120[nm]. Therfore all transistors will have a width of 240[nm]

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/nand-schematic.png}
	\caption{Two-input CMOS NAND gate schematic}
	\label{fig:nand-schematic}
\end{figure}

\section{Conclusion}
The workflow implemented enables the rapid re-use of circuits. This concept is important as it is not feasible to lay out every MOSFET and every connection in a larger design. By building up a design from previously designed components, keeping track of the characteristics of each piece along the way, it is much easier to create complex digital circuits.

This process is the essence of VLSI. It is not possible for people to build a CPU with millions or billions of transistors one MOSFET at a time. Very large scale designs are only made possible by slowly building up a subsystem by using repeatable elements, and abstracting away the fine details.

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