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\font\myfont=cmr12 at 15pt 
\title{\myfont VLSI Labs 1\&2 \\ Simple MOSFET \& CMOS Inverter Trends}
\author{Aidan Sharpe}

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\begin{document}
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\section{Introduction}
While they are commonly treated as three-terminal devices in introductory electronics classes, MOSFETs are actually four-terminal devices. In discrete, three-terminal designs, the body pin and the source pin are tied together internally. In CMOS VLSI design, all four pins play an important role. Having a discrete body pin provides each transistor with its own power or ground reference depending on the type of MOSFET. 

In CMOS VLSI design, there are two types of complementary MOSFETs, hence the name CMOS. The two types are the n-channel MOSFET (NMOS) and the p-channel MOSFET (PMOS). N-channel MOSFETs behave like a switch that is normally open, while p-channel MOSFETs behave like a normally closed switch. To change the state of the switch, a voltage $V_{gs}$ is applied to the gate pin.

We will discuss the exact behavior of the two types of MOSFETs further throughout the following two sections. In the final section, we will explore and discuss the properties and behaviors of a CMOS inverter.

\section{NMOS Characteristics}
The Shockley first-order model is a good approximation of the relationship between the input voltages to and the current through a MOSFET. The model approximates the current through an NMOS $I_{ds}$ as
\begin{equation}
	I_{ds} = \begin{cases}
		0 & V_{gs} < V_t \\
		\beta \left(V_{gs} - V_t - \frac{V_{ds}}{2}\right) V_{ds} & V_{ds} < V_{dsat} \\
		\frac{\beta}{2}\left(V_{gs} - V_t\right)^2 & V_{ds} > V_{dsat}
	\end{cases}
	\label{eqn:nmos-shockley-first-order}
\end{equation}
where $V_{gs}$ is the voltage between the gate and source, $V_t$ is the threshold voltage, $V_{ds}$ is the voltage between the drain and the source, $V_{dsat} = V_{gs} - V_t$, and $\beta$ is a constant based on the physical properties of the MOSFET. 

We parametrically varied $V_{gs}$ and $V_{ds}$ using a Python script. Then, we plotted $I_{ds}$ using the model described in equation \ref{eqn:nmos-shockley-first-order}. Seen in figure \ref{fig:nmos-shockley-first-order}, increasing $V_{gs}$ will increase the current. Furthermore, increasing $V_{ds}$ will also increase the current, but only up to a point. After reaching that point, the current does not change with $V_{ds}$.

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/simulated-iv-curves.png}
	\caption{Plot of Shockley first order model for an n-channel MOSFET}
	\label{fig:nmos-shockley-first-order}
\end{figure}

We then used a simulation tool that takes into account the non-ideal effects of MOSFETs to provide a more accurate plot of the relationship between input voltages and current. First, an NMOS was placed in the schematic, along with some voltage sources with variable voltages. It is important that the voltages be variable, so a parametric test may be run. The final schematic is seen in figure \ref{fig:nmos-iv-schematic}.

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/nmos-iv-schematic.png}
	\caption{NMOS parametric test schematic}
	\label{fig:nmos-iv-schematic}
\end{figure}

For the simulation, we set up our output to be the current at the positive terminal of the voltage source V2. We ran a DC sweep simulation of $V_{ds}$, while parametrically stepping through values of $V_{gs}$. The resulting plot is seen in figure \ref{fig:nmos-simulation-results}.

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/iv-curves.png}
	\caption{Simulated relationship between input voltage and NMOS current}
	\label{fig:nmos-simulation-results}
\end{figure}

There is clearly some resemblance between the Shockley model plot and the simulated results. One important difference is that the curves flatten out completely in the Shockley model, while the traces in the simulated NMOS continue to increase well into the saturation region.


\section{PMOS Characteristics}
While the source of an NMOS is tied to ground, the source of a PMOS is tied to power. 

\begin{aside}{Voltage Naming Conventions}
	The 'D' in $V_{DD}$ actually stands for "drain" despite connecting to the source of the PMOS. Furthermore, the 'S' in $V_{SS}$ does connect to the source pin of the NMOS. This naming convention dates back to a time when BJT logic was the norm. Specifically, NPN BJT logic. With NPNs, the collector is at the most positive voltage, hence the name $V_{CC}$ corresponding to power. When FET logic became popular, the naming scheme remained the same, but with drains and sources in place of collectors and emitters. Hence, $V_{DD}$ became the name for power, and $V_{SS}$ became the name for ground\cite{VddNaming}.
\end{aside}

PMOS transistors behave the same as NMOS, with the signs of all the voltages and currents flipped\cite{VLSICircuitsSystems}. It is also important to note that by changing the signs, the inequalities flip as well, meaning that quantities that must be greater than others for an NMOS are now required to be less, and vice versa. Therefore, the Shockley model for the current through a PMOS is
\begin{equation}
	I_{ds} = \begin{cases}
		0 & V_{gs} > V_t \\
		-\beta \left(V_{gs} - V_t - \frac{V_{ds}}{2}\right) V_{ds} & V_{ds} > V_{dsat} \\
		-\frac{\beta}{2}\left(V_{gs} - V_t\right)^2 & V_{ds} < V_{dsat}
	\end{cases}.
	\label{eqn:pmos-shockley-first-order}
\end{equation}

With this knowledge, we modified our Python script to model a PMOS. The Shockley model plot seen in figure \ref{fig:pmos-shockley} has the same shape as the plot for the NMOS, but rotated $180^\circ$ about the origin. 

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/pmos-shockley-model.png}
	\caption{Plot of Shockley first order model for a p-channel MOSFET}
	\label{fig:pmos-shockley}
\end{figure}

Again, we compared the Shockley model against simulation results. In our schematic, the voltage source for $V_{gs}$ was tied to power instead of ground, and the voltage source for $V_{ds}$ was rotated $180^\circ$. Furthermore, the body pin of the PMOS was tied to power instead of ground. All of these changes are reflected in the PMOS test schematic seen in figure \ref{fig:pmos-iv-schematic}.

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/pmos-iv-schematic.png}
	\caption{PMOS parametric test schematic}
	\label{fig:pmos-iv-schematic}
\end{figure}

Finally, we ran the simulation, this time measuring the current at the drain pin of the PMOS. We swept $V_{ds}$ from -2V to 0V with a step size of 0.1V, and parametrically swept $V_{gs}$ from -2.5V to 0V with a step size of 0.25V. The result was a similar plot to the NMOS simulation, again, rotated $180^\circ$ about the origin, as seen in figure \ref{fig:pmos-iv-simulation}. Another difference between the NMOS and PMOS simulations is the actual values of the current. While the shapes are similar, the absolute value of the PMOS current is less than the NMOS current for the same absolute value of the voltage inputs.

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/pmos-iv-2.png}
	\caption{Simulated relationship between input voltages and PMOS current}
	\label{fig:pmos-iv-simulation}
\end{figure}

\section{The Noise Margin}
The noise margin is the amount of noise that a CMOS circuit can withstand without compromising the operation of the circuit\cite{VLSISystemDesign}. This region is necessary to create a buffer that prevents small amounts of noise from affecting the logic state. There are two noise margins: noise margin high (NM\textsubscript{H}) and noise margin low (NM\textsubscript{L}). 

The two noise margins are defined in terms of four key voltages on the voltage transfer curve (VTC) seen in figure \ref{fig:inv_vtc}: $V_\text{IL}$, $V_\text{IH}$, $V_\text{OL}$, and $V_\text{OH}$. $V_\text{IL}$ is defined as the lower input voltage where the slope of the VTC is -1, and $V_\text{IH}$ is defined as the upper input voltage meeting the same requirement. $V_\text{OL}$ is defined as the output voltage when the input voltage is equal to $V_\text{IH}$, and similarly, $V_\text{OH}$ is defined as the output voltage when the input voltage is equal to $V_\text{IL}$.

Practically speaking, when the input voltage is between $V_{OL}$ and $V_{IL}$ it is interpreted as logic low, and when the input voltage is between $V_{IH}$ and $V_{OH}$ it is interpreted as logic high. The region between $V_{IL}$ and $V_{IH}$ is the ``undefined region", where the logic state is unclear \cite{VLSISystemDesign}.

\begin{figure}[h]
	\center
	\includegraphics[width=0.4\textwidth]{graphics/inverter-noise-margin.png}
	\caption{The VTC and its derivative for a CMOS inverter with $w_p=240$[nm] and $w_n=120$[nm]}
	\label{fig:inv_vtc}.
\end{figure}

We pulled the VTC into a calculator tool, and implemented the definitions for the different voltages associated with the noise margin. Evaluating the expressions produced the values seen in table \ref{tbl:vtc-voltages}.

\begin{table}[H]
\center
\caption{Important VTC voltages}
\begin{tabular}{c | c}
	$V_\text{IL}$ & 2.357[V] \\
	\hline
	$V_\text{IH}$ & 3.531[V] \\
	\hline
	$V_\text{OL}$ & 0.683[V] \\
	\hline
	$V_\text{OH}$ & 4.118[V] \\
\end{tabular}
\label{tbl:vtc-voltages}
\end{table}

With these voltages now defined, the noise margin high was calculated using
\begin{equation}
	\text{NM}_\text{H} = V_\text{OH} - V_\text{IH},
\end{equation}
and noise margin low was calculated with
\begin{equation}
	\text{NM}_\text{L} = V_\text{IL} - V_\text{OL}.
\end{equation}
Therefore, $\text{NM}_\text{H} = 0.587$[V] and $\text{NM}_\text{L} = 1.674$[V]. Any voltage existing within the high noise margin would be interpreted as a logic 1 for this inverter, and any voltage existing within the low noise margin would be interpreted as a logic 0. By definition, the larger the noise margin, the more noise the signal can handle without affecting the logic state. Therefore, this inverter can handle more noise when in the logic low state than in the logic high state. 

The noise margin is not the same for all inverters, however. To see how the noise margin changes when the MOSFETs used are sized differently, a parametric test was conducted. The width of the NMOS was held constant at 120[nm], but the width of the PMOS was parametrically varied from 120[nm] to 360[nm] with 5 steps in a logarithmic sweep. The resulting VTC is seen in figure \ref{fig:inv-parametric-vtc}. This test produced six traces, where the inverter switched at different input voltages, depending on the width of the PMOS.

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/inv-parametric-nm-1.png}
	\caption{Inverter VTC for different widths of the PMOS}
	\label{fig:inv-parametric-vtc}
\end{figure}

Again, the VTC was pulled into a calculator tool to determine the derivative, and ultimately, the four voltages associated with the noise margin. Since there were six traces, the result was six derivatives, and a range of values for $V_{OH}$, $V_{IH}$, $V_{OL}$, and $V_{IL}$. The four important voltages were plotted as a function of the width of the PMOS $w_p$, seen in figure \ref{fig:inv-parametric-nm-voltages}.

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/inv-parametric-nm-4.png}
	\caption{$V_{OH}$ (green), $V_{IH}$ (yellow), $V_{OL}$ (cyan), and $V_{IL}$ (red) as a function of $w_p$.}
	\label{fig:inv-parametric-nm-voltages}
\end{figure}

Finally, the noise margins were calculated at each $w_p$ using the four already calculated voltages, and the results were plotted in figure \ref{fig:inv-parametric-nm}. The high noise margin shrinks as $w_p$ increases, while the low noise margin grows. However, the sum of $\text{NM}_\text{L}$ and $\text{NM}_\text{H}$ remains roughly constant, although there is a dip with a minimum where the two noise margins are the same. This means that although the individual noise margins change, the size of the undefined region between logic high and logic low remains about the same.

\begin{figure}[h]
	\center\includegraphics[width=0.4\textwidth]{graphics/inv-parametric-nm-3.png}
	\caption{Resulting $\text{NM}_\text{L}$ (yellow) and $\text{NM}_\text{H}$ (red).}
	\label{fig:inv-parametric-nm}
\end{figure}

\section{Conclusion}
A common theme between analyzing the current through a MOSFET and analyzing the noise margin is the dependence on the physical properties of the MOSFETs. The Shockley model describes the effect of the physical properties by packaging them nicely into the $\beta$ term. However, the Shockley model does not take into account any non-ideal effects, which are also based on physical properties of the device.

Going forward, it will be important to fully understand how physical properties affect the behavior of individual MOSFETs as well as entire circuits. In doing so, designs may be fine-tuned to increase speed and minimize losses.
\printbibliography
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