Pretty much all of Fall 2024

7th-Semester-Fall-2024/VLSI/homework/homework-9/homework-9.md

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+# Homework 9 - Aidan Sharpe
+
+## Problem 1
+Find the best width and spacing to minimize the RC delay of a metal2 bus in a 180[nm] procecss if the pitch cannot exceed 960[nm]. Minimum width and spacing are 320[nm]. First, assume that neither adjacent bit is switching. How does your anwer change if the adjacent bits may be switching?
+
+### Not Switching
+When the bits are not switching, the speed is dependent on minimizing $R$. $R$ is smallest when $w$ is largest. If $s$ must be at least 320[nm] and $s+w$ must be no more than 960[nm], then the largest $w$ can be is 640[nm]. Therefore, the optimal pair is $s=320$[nm] and $w=640$[nm].
+
+### Switching
+When the bits are switching, the speed is dependent on minimizing the time constant $RC$. Estimating the value for $C$ from Figure 6.12, yields $s=480$[nm] and $w=480$[nm] to be optimal for minimizing the delay for switching bits.

7th-Semester-Fall-2024/VLSI/homework/homework-9/optimal.py

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+import numpy as np
+import matplotlib.pyplot as plt
+
+w = np.array([320, 480, 640])
+C_s_320 = np.array([220, 230, 240])
+C_s_480 = np.array([165, 170, 175])
+C_s_640 = np.array([140, 145, 155])
+
+R_s_320 = C_s_320/w
+R_s_480 = C_s_480/w
+R_s_640 = C_s_640/w
+
+print(R_s_320)
+print(R_s_480)
+print(R_s_640)
+
+
+#eps_0 = 8.854E-12   # F/m
+#t_ox = 0.7E-6       # m
+#C_fringe = 0.05E-9  # F/m
+#w_min = 320E-9
+#
+#w = np.arange(w_min, 2.1*w_min, w_min/2)
+##s = 3*w_min - w
+#s = 640
+#
+#k_vert = 4.1
+#k_horiz = 3.9
+#
+#C_total = eps_0 * ( 2*k_vert*w/h + 2*k_horiz*t/s ) + C_fringe
+#print(C_total)