Major progress on VLSI lab 1&2 and ECOMMS lab 1

6th-Semester-Spring-2024/DSP/Labs/FinalProject/adding_noise.py

@@ -133,7 +133,7 @@ def calculate_pesqs(all_signals, all_noises, sample_rate, snrs):
                 noisy_signal = add_noise(signal_data, noise_data, snr)
                 filtered_signal = enhanced(noisy_signal, sample_rate)
                 #wavfile.write(f"noisy/sp{j+1:02}_{noises[i]}_snr{snr}.wav", sample_rate, )
-                #sd.play(normalize_signal(signal_data), samplerate=sample_rate, blocking=True)
+                sd.play(normalize_signal(signal_data), samplerate=sample_rate, blocking=True)
                 #sd.play(normalize_signal(noisy_signal), samplerate=sample_rate, blocking=True)
                 #sd.play(normalize_signal(filtered_signal), samplerate=sample_rate, blocking=True)
             
@@ -151,7 +151,9 @@ def main():
     snrs = (0, 10, 20, 30)
 
     # Load all signals and all noises
+    print("loading signals")
     signal_sample_rate, all_signals = load_all_signals()
+    print("loading noise")
     noise_sample_rate, all_noises = load_all_noises()
 
     assert signal_sample_rate == noise_sample_rate, "Signal and noise sampling rates didn't match."

7th-Semester-Fall-2024/ECOMMS/labs/lab1/part3.py

@@ -1,11 +1,74 @@
 import numpy as np
 import matplotlib.pyplot as plt
+import matplotlib as mpl
+from cycler import cycler
 import scipy as sp
 
-f_m = 5E3
-f_c = 25E3
 
-f_s = 50*f_c
+def add_noise(s, SNR):
+    var_s = np.cov(s)
+    var_noise = var_s/(10**(SNR/10))
+    noise = var_noise**0.5 * np.random.randn(len(s))
+    return s + noise
+
+def plot_at_snrs(t, f, s_am, s_fm):
+    stem_colors = ['k', 'b', 'r']
+    ci = 0
+    stem_color = stem_colors[ci]
+
+    am_time = plt.figure()
+    am_freq = plt.figure()
+    fm_time = plt.figure()
+    fm_freq = plt.figure()
+
+    for SNR in range(10,30,10):
+        m_am = add_noise(s_am,SNR)
+        m_fm = add_noise(s_fm,SNR)
+
+        plt.figure(am_time)
+        plt.plot(t, m_am, label=f"SNR = {SNR}")
+
+        plt.figure(am_freq)
+        plt.stem(f, abs(sp.fft.fft(m_am)), label=f"SNR = {SNR}", markerfmt=stem_color+"o", linefmt=stem_color+"-")
+
+        plt.figure(fm_time)
+        plt.plot(t, m_fm, label=f"SNR = {SNR}")
+
+        plt.figure(fm_freq)
+        plt.stem(f, abs(sp.fft.fft(m_fm)), label=f"SNR = {SNR}", markerfmt=stem_color+"o", linefmt=stem_color+"-")
+
+        ci += 1
+        stem_color = stem_colors[ci]
+
+    plt.figure(am_time)
+    plt.plot(t, s_am, label="Pure signal")
+    plt.legend(loc="upper right")
+    plt.savefig("part-3-am-time")
+
+    plt.figure(am_freq)
+    plt.stem(f, abs(sp.fft.fft(s_am)), label="Pure signal", markerfmt=stem_color+"o", linefmt=stem_color+"-")
+    plt.xlim((0, 2E5))
+    plt.legend(loc="upper right")
+    plt.savefig("part-3-am-freq")
+
+    plt.figure(fm_time)
+    plt.plot(t, s_fm, label="Pure signal")
+    plt.legend(loc="upper right")
+    plt.savefig("part-3-fm-time")
+
+    plt.figure(fm_freq)
+    plt.stem(f, abs(sp.fft.fft(s_fm)), label="Pure signal", markerfmt=stem_color+"o", linefmt=stem_color+"-")
+    plt.xlim((0, 2E5))
+    plt.legend(loc="upper right")
+    plt.savefig("part-3-fm-freq")
+
+    plt.show()
+
+
+def main():
+    f_m = 5E3
+    f_c = 125E3
+    f_s = 125E4
 
     T_m = 1/f_m
     T_c = 1/f_c
@@ -14,41 +77,17 @@ T_s = 1/f_s
     A_c = 10
     A_m = 1
 
-t = np.arange(0,2*T_m,T_s)
+    t = np.arange(0,2*T_m,T_s)      # Time domain
-f = t*f_s/(2*T_m)
+    f = t*f_s/(2*T_m)               # Frequency domain
 
-# ===== AM =====
+    beta_f = 10                     # Modulation index
-s = A_c * (1 + A_m*np.cos(2*np.pi*f_m*t)) * np.cos(2*np.pi*f_c*t)
 
-var_s = np.cov(s)
+    s_am = A_c * (1 + A_m*np.cos(2*np.pi*f_m*t)) * np.cos(2*np.pi*f_c*t)
+    s_fm = A_c*np.cos(2*np.pi*f_c*t + beta_f*A_m*np.sin(2*np.pi*f_m*t))
+    plot_at_snrs(t, f, s_am, s_fm)
 
-SNR = 10
-var_snr = var_s/(10**(SNR/10))
-noise_snr = (var_snr**0.5) * np.random.randn(len(s))
-m = s+noise_snr
 
-S = sp.fft.fft(s)
-M = sp.fft.fft(m)
 
-plt.subplot(211)
+if __name__ == "__main__":
-plt.stem(f, S)
+    mpl.rcParams['axes.prop_cycle'] = cycler(color=['k', 'b', 'r'])
-plt.subplot(212)
+    main()
-plt.stem(f, M)
-plt.show()
-
-# ===== FM =====
-beta_f = 10
-s = A_c*np.cos(2*np.pi*f_c*t + beta_f*A_m*np.sin(2*np.pi*f_m*t))
-
-var_snr = var_s/(10**(SNR/10))
-noise_snr = (var_snr**0.5) * np.random.randn(len(s))
-m = s+noise_snr
-
-S = sp.fft.fft(s)
-M = sp.fft.fft(m)
-
-plt.subplot(211)
-plt.stem(f, S)
-plt.subplot(212)
-plt.stem(f, M)
-plt.show()

7th-Semester-Fall-2024/ECOMMS/labs/lab1/part4.py

@@ -0,0 +1 @@
+

7th-Semester-Fall-2024/VLSI/homework/homework-1/problem_1.py

@@ -14,19 +14,19 @@ L = 0.6
 
 beta = mu * C_ox * W/L
 
-V_g_range = np.arange(6)
+V_g_range = np.arange(-5,1)
 V_t = 0.7
-V_dd = np.linspace(0, 5, 50)
+V_dd = np.linspace(-5,0, 50)
 
 def I_ds(V_gs, V_ds, V_t, beta):
-    if V_gs < V_t:
+    if V_gs > V_t:
         return np.zeros_like(V_ds)
 
     V_dsat = V_gs - V_t
 
-    return np.where(V_ds < V_dsat,
+    return np.where(V_ds > V_dsat,
-                    beta * (V_gs - V_t - V_ds/2) * V_ds, 
+                    -beta * (V_gs - V_t - V_ds/2) * V_ds, 
-                    beta * (V_gs - V_t)**2 / 2)
+                    -beta * (V_gs - V_t)**2 / 2)
 
 for V_s in (0, 2):
     for V_g in V_g_range:

7th-Semester-Fall-2024/VLSI/labs/lab-1-2/lab-1-2.aux

@@ -13,7 +13,15 @@
 \gdef\HyperFirstAtBeginDocument#1{#1}
 \providecommand\HyField@AuxAddToFields[1]{}
 \providecommand\HyField@AuxAddToCoFields[2]{}
-\citation{VLSI_System_Design}
+\abx@aux@refcontext{nty/global//global/global}
+\abx@aux@cite{0}{VddNaming}
+\abx@aux@segm{0}{0}{VddNaming}
+\abx@aux@cite{0}{VLSICircuitsSystems}
+\abx@aux@segm{0}{0}{VLSICircuitsSystems}
+\abx@aux@cite{0}{VLSISystemDesign}
+\abx@aux@segm{0}{0}{VLSISystemDesign}
+\abx@aux@cite{0}{VLSISystemDesign}
+\abx@aux@segm{0}{0}{VLSISystemDesign}
 \@writefile{toc}{\contentsline {section}{\numberline {I}Introduction}{2}{section.1}\protected@file@percent }
 \@writefile{toc}{\contentsline {section}{\numberline {II}NMOS Characteristics}{2}{section.2}\protected@file@percent }
 \newlabel{eqn:nmos-shockley-first-order}{{1}{2}{NMOS Characteristics}{equation.2.1}{}}
@@ -21,10 +29,30 @@
 \newlabel{fig:nmos-shockley-first-order}{{1}{2}{Plot of Shockley first order model for an n-channel MOSFET}{figure.1}{}}
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 \newlabel{fig:nmos-iv-schematic}{{2}{2}{NMOS parametric test schematic}{figure.2}{}}
-\@writefile{toc}{\contentsline {section}{\numberline {III}The Noise Margin}{2}{section.3}\protected@file@percent }
+\@writefile{toc}{\contentsline {section}{\numberline {III}PMOS Characteristics}{2}{section.3}\protected@file@percent }
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+\@writefile{lof}{\contentsline {figure}{\numberline {3}{\ignorespaces Simulated relationship between input voltage and NMOS current}}{3}{figure.3}\protected@file@percent }
-\newlabel{fig:inv_vtc}{{3}{3}{The VTC and its derivative for a CMOS inverter with $w_p=240$[nm] and $w_n=120$[nm]}{figure.3}{}}
+\newlabel{fig:nmos-simulation-results}{{3}{3}{Simulated relationship between input voltage and NMOS current}{figure.3}{}}
-\@writefile{lot}{\contentsline {table}{\numberline {I}{\ignorespaces Important VTC voltages}}{3}{table.1}\protected@file@percent }
+\newlabel{eqn:pmos-shockley-first-order}{{2}{3}{PMOS Characteristics}{equation.3.2}{}}
-\@writefile{toc}{\contentsline {section}{\numberline {IV}Discussion}{3}{section.4}\protected@file@percent }
+\@writefile{lof}{\contentsline {figure}{\numberline {4}{\ignorespaces Plot of Shockley first order model for a p-channel MOSFET}}{3}{figure.4}\protected@file@percent }
-\@writefile{toc}{\contentsline {section}{\numberline {V}Conclusion}{3}{section.5}\protected@file@percent }
+\newlabel{fig:pmos-shockley}{{4}{3}{Plot of Shockley first order model for a p-channel MOSFET}{figure.4}{}}
-\gdef \@abspage@last{2}
+\@writefile{lof}{\contentsline {figure}{\numberline {5}{\ignorespaces PMOS parametric test schematic}}{3}{figure.5}\protected@file@percent }
+\newlabel{fig:pmos-iv-schematic}{{5}{3}{PMOS parametric test schematic}{figure.5}{}}
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+\@writefile{lof}{\contentsline {figure}{\numberline {7}{\ignorespaces The VTC and its derivative for a CMOS inverter with $w_p=240$[nm] and $w_n=120$[nm]}}{4}{figure.7}\protected@file@percent }
+\newlabel{fig:inv_vtc}{{7}{4}{The VTC and its derivative for a CMOS inverter with $w_p=240$[nm] and $w_n=120$[nm]}{figure.7}{}}
+\@writefile{lot}{\contentsline {table}{\numberline {I}{\ignorespaces Important VTC voltages}}{4}{table.1}\protected@file@percent }
+\newlabel{tbl:vtc-voltages}{{I}{4}{Important VTC voltages}{table.1}{}}
+\@writefile{lof}{\contentsline {figure}{\numberline {8}{\ignorespaces Inverter VTC for different widths of the PMOS}}{4}{figure.8}\protected@file@percent }
+\newlabel{fig:inv-parametric-vtc}{{8}{4}{Inverter VTC for different widths of the PMOS}{figure.8}{}}
+\@writefile{lof}{\contentsline {figure}{\numberline {9}{\ignorespaces $V_{OH}$ (green), $V_{IH}$ (yellow), $V_{OL}$ (cyan), and $V_{IL}$ (red) as a function of $w_p$.}}{4}{figure.9}\protected@file@percent }
+\newlabel{fig:inv-parametric-nm-voltages}{{9}{4}{$V_{OH}$ (green), $V_{IH}$ (yellow), $V_{OL}$ (cyan), and $V_{IL}$ (red) as a function of $w_p$}{figure.9}{}}
+\@writefile{lof}{\contentsline {figure}{\numberline {10}{\ignorespaces Resulting $\text  {NM}_\text  {L}$ (yellow) and $\text  {NM}_\text  {H}$ (red).}}{4}{figure.10}\protected@file@percent }
+\newlabel{fig:inv-parametric-nm}{{10}{4}{Resulting $\text {NM}_\text {L}$ (yellow) and $\text {NM}_\text {H}$ (red)}{figure.10}{}}
+\@writefile{toc}{\contentsline {section}{\numberline {V}Conclusion}{4}{section.5}\protected@file@percent }
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+\abx@aux@defaultrefcontext{0}{VLSICircuitsSystems}{nty/global//global/global}
+\abx@aux@defaultrefcontext{0}{VLSISystemDesign}{nty/global//global/global}
+\gdef \@abspage@last{4}

7th-Semester-Fall-2024/VLSI/labs/lab-1-2/lab-1-2.bbl

@@ -0,0 +1,89 @@
+% $ biblatex auxiliary file $
+% $ biblatex bbl format version 3.2 $
+% Do not modify the above lines!
+%
+% This is an auxiliary file used by the 'biblatex' package.
+% This file may safely be deleted. It will be recreated by
+% biber as required.
+%
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+\makeatletter
+\@ifundefined{ver@biblatex.sty}
+  {\@latex@error
+     {Missing 'biblatex' package}
+     {The bibliography requires the 'biblatex' package.}
+      \aftergroup\endinput}
+  {}
+\endgroup
+
+
+\refsection{0}
+  \datalist[entry]{nty/global//global/global}
+    \entry{VddNaming}{online}{}
+      \name{author}{1}{}{%
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+      \strng{fullhash}{c79d5231b092430b3f8b61ce3f9f9f2b}
+      \strng{bibnamehash}{c79d5231b092430b3f8b61ce3f9f9f2b}
+      \strng{authorbibnamehash}{c79d5231b092430b3f8b61ce3f9f9f2b}
+      \strng{authornamehash}{c79d5231b092430b3f8b61ce3f9f9f2b}
+      \strng{authorfullhash}{c79d5231b092430b3f8b61ce3f9f9f2b}
+      \field{sortinit}{L}
+      \field{sortinithash}{7c47d417cecb1f4bd38d1825c427a61a}
+      \field{labelnamesource}{author}
+      \field{labeltitlesource}{title}
+      \field{title}{What is the difference between VCC, VDD, VEE, VSS}
+      \field{year}{2011}
+      \verb{urlraw}
+      \verb https://electronics.stackexchange.com/questions/17382/what-is-the-difference-between-v-cc-v-dd-v-ee-v-ss
+      \endverb
+      \verb{url}
+      \verb https://electronics.stackexchange.com/questions/17382/what-is-the-difference-between-v-cc-v-dd-v-ee-v-ss
+      \endverb
+    \endentry
+    \entry{VLSICircuitsSystems}{book}{}
+      \name{author}{1}{}{%
+        {{hash=7bdab0d2054f0c60f1ba24c3bdf19a4f}{%
+           family={Neil\bibnamedelimb H.\bibnamedelimi E.\bibnamedelimi Weste},
+           familyi={N\bibinitperiod\bibinitdelim H\bibinitperiod\bibinitdelim E\bibinitperiod\bibinitdelim W\bibinitperiod},
+           given={David\bibnamedelimb Money\bibnamedelima Harris},
+           giveni={D\bibinitperiod\bibinitdelim M\bibinitperiod\bibinitdelim H\bibinitperiod}}}%
+      }
+      \list{publisher}{1}{%
+        {Pearson}%
+      }
+      \strng{namehash}{7bdab0d2054f0c60f1ba24c3bdf19a4f}
+      \strng{fullhash}{7bdab0d2054f0c60f1ba24c3bdf19a4f}
+      \strng{bibnamehash}{7bdab0d2054f0c60f1ba24c3bdf19a4f}
+      \strng{authorbibnamehash}{7bdab0d2054f0c60f1ba24c3bdf19a4f}
+      \strng{authornamehash}{7bdab0d2054f0c60f1ba24c3bdf19a4f}
+      \strng{authorfullhash}{7bdab0d2054f0c60f1ba24c3bdf19a4f}
+      \field{sortinit}{N}
+      \field{sortinithash}{22369a73d5f88983a108b63f07f37084}
+      \field{labelnamesource}{author}
+      \field{labeltitlesource}{title}
+      \field{title}{CMOS VLSI Design a Circuits and Systems Perspective, Fourth Edition}
+      \field{year}{2011}
+    \endentry
+    \entry{VLSISystemDesign}{online}{}
+      \field{sortinit}{N}
+      \field{sortinithash}{22369a73d5f88983a108b63f07f37084}
+      \field{labeltitlesource}{title}
+      \field{title}{Noise Margin}
+      \field{year}{2017}
+      \verb{urlraw}
+      \verb https://www.vlsisystemdesign.com/noise-margin/
+      \endverb
+      \verb{url}
+      \verb https://www.vlsisystemdesign.com/noise-margin/
+      \endverb
+    \endentry
+  \enddatalist
+\endrefsection
+\endinput
+

7th-Semester-Fall-2024/VLSI/labs/lab-1-2/lab-1-2.bbl-SAVE-ERROR

@@ -0,0 +1,38 @@
+% $ biblatex auxiliary file $
+% $ biblatex bbl format version 3.2 $
+% Do not modify the above lines!
+%
+% This is an auxiliary file used by the 'biblatex' package.
+% This file may safely be deleted. It will be recreated by
+% biber as required.
+%
+\begingroup
+\makeatletter
+\@ifundefined{ver@biblatex.sty}
+  {\@latex@error
+     {Missing 'biblatex' package}
+     {The bibliography requires the 'biblatex' package.}
+      \aftergroup\endinput}
+  {}
+\endgroup
+
+
+\refsection{0}
+  \datalist[entry]{nty/global//global/global}
+    \entry{VLSISystemDesign}{online}{}
+      \field{sortinit}{N}
+      \field{sortinithash}{22369a73d5f88983a108b63f07f37084}
+      \field{labeltitlesource}{title}
+      \field{title}{Noise Margin}
+      \field{year}{2017}
+      \verb{urlraw}
+      \verb https://www.vlsisystemdesign.com/noise-margin/
+      \endverb
+      \verb{url}
+      \verb https://www.vlsisystemdesign.com/noise-margin/
+      \endverb
+    \endentry
+  \enddatalist
+\endrefsection
+\endinput
+

7th-Semester-Fall-2024/VLSI/labs/lab-1-2/lab-1-2.blg

@@ -0,0 +1,15 @@
+[0] Config.pm:307> INFO - This is Biber 2.19
+[0] Config.pm:310> INFO - Logfile is 'lab-1-2.blg'
+[117] biber:340> INFO - === Wed Nov 13, 2024, 11:58:45
+[137] Biber.pm:419> INFO - Reading 'lab-1-2.bcf'
+[225] Biber.pm:979> INFO - Found 3 citekeys in bib section 0
+[241] Biber.pm:4419> INFO - Processing section 0
+[255] Biber.pm:4610> INFO - Looking for bibtex file 'references.bib' for section 0
+[256] bibtex.pm:1713> INFO - LaTeX decoding ...
+[259] bibtex.pm:1519> INFO - Found BibTeX data source 'references.bib'
+[314] UCollate.pm:68> INFO - Overriding locale 'en-US' defaults 'normalization = NFD' with 'normalization = prenormalized'
+[314] UCollate.pm:68> INFO - Overriding locale 'en-US' defaults 'variable = shifted' with 'variable = non-ignorable'
+[314] Biber.pm:4239> INFO - Sorting list 'nty/global//global/global' of type 'entry' with template 'nty' and locale 'en-US'
+[314] Biber.pm:4245> INFO - No sort tailoring available for locale 'en-US'
+[324] bbl.pm:660> INFO - Writing 'lab-1-2.bbl' with encoding 'UTF-8'
+[325] bbl.pm:763> INFO - Output to lab-1-2.bbl

7th-Semester-Fall-2024/VLSI/labs/lab-1-2/lab-1-2.fdb_latexmk

@@ -1,5 +1,12 @@
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+  "lab-1-2.bcf" 1731522051.43047 107981 f29da5bcd9833ccaa4cc6be31fd38999 "pdflatex"
+  "references.bib" 1731470232.82083 558 df972a2d65f28e8a8ecebb4ee0b82d70 ""
+  (generated)
+  "lab-1-2.bbl"
+  "lab-1-2.blg"
+  (rewritten before read)
+["pdflatex"] 1731522048.40538 "lab-1-2.tex" "lab-1-2.pdf" "lab-1-2" 1731522051.68977 0
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7th-Semester-Fall-2024/VLSI/labs/lab-1-2/lab-1-2.fls

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 ** Conference Paper **
 Before submitting the final camera ready copy, remember to:
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7th-Semester-Fall-2024/VLSI/labs/lab-1-2/lab-1-2.tex

@@ -26,11 +26,28 @@
 \usepackage{lmodern}
 \usepackage{datetime}
 \usepackage{ragged2e}
+\usepackage[backend=biber]{biblatex}
 \input{border.tex}
 \pgfpagesuselayout{boxed}
 
+\newenvironment{aside}[1]
+    {\begin{center}
+    \begin{tabular}{|p{0.4\textwidth}|}
+    \hline\\
+	\begin{center}
+	\textbf{#1---An Aside}\\
+	\end{center}
+	}
+	{
+    \\\\\hline
+    \end{tabular} 
+    \end{center}
+	}
+
 \hyphenation{op-tical net-works semi-conduc-tor}% correct bad hyphenation here
 
+\addbibresource{references.bib}
+
 \font\myfont=cmr12 at 15pt 
 \title{\myfont VLSI Labs 1\&2 \\ Simple MOSFET \& CMOS Inverter Trends}
 \author{Aidan Sharpe}
@@ -43,14 +60,14 @@
 \maketitle
 
 \section{Introduction}
-While they are commonly treated as three-terminal devices in introductory electronics classes, MOSFETs are actually four-terminal devices. In discrete, three-terminal designs, the body pin and the source pin are tied together internally. In CMOS VLSI desin, all four pins play an important role. Having a discrete body pin provides each transistor with its own power or ground reference depending on the type of MOSFET. 
+While they are commonly treated as three-terminal devices in introductory electronics classes, MOSFETs are actually four-terminal devices. In discrete, three-terminal designs, the body pin and the source pin are tied together internally. In CMOS VLSI design, all four pins play an important role. Having a discrete body pin provides each transistor with its own power or ground reference depending on the type of MOSFET. 
 
 In CMOS VLSI design, there are two types of complementary MOSFETs, hence the name CMOS. The two types are the n-channel MOSFET (NMOS) and the p-channel MOSFET (PMOS). N-channel MOSFETs behave like a switch that is normally open, while p-channel MOSFETs behave like a normally closed switch. To change the state of the switch, a voltage $V_{gs}$ is applied to the gate pin.
 
-We will discuss the exact behavior of the two types of MOSFETs further throughout the following two sections. In the final section, we will explore and discuss the properies and behaviors of a CMOS inverter.
+We will discuss the exact behavior of the two types of MOSFETs further throughout the following two sections. In the final section, we will explore and discuss the properties and behaviors of a CMOS inverter.
 
 \section{NMOS Characteristics}
-The Shockley first-order model is a good approximation of the relationship between the input voltages and the current through a MOSFET. The model approximates the current trhough an NMOS $I_{ds}$ is
+The Shockley first-order model is a good approximation of the relationship between the input voltages and the current through a MOSFET. The model approximates the current through an NMOS $I_{ds}$ is
 \begin{equation}
 	I_{ds} = \begin{cases}
 		0 & V_{gs} < V_t \\
@@ -63,44 +80,101 @@ where $V_{gs}$ is the voltage between the gate and source, $V_t$ is the threshol
 
 We parametrically varied $V_{gs}$ and $V_{ds}$ using a Python. Then, we plotted $I_{ds}$ using the model described in equation \ref{eqn:nmos-shockley-first-order}. Seen in figure \ref{fig:nmos-shockley-first-order}, increasing $V_{gs}$ will increase the current. Furthermore, increasing $V_{ds}$ will also increase the current, but only up to a point. After reaching that point, the current does not change with $V_{ds}$.
 
-\begin{figure}[H]
+\begin{figure}[h]
 	\center\includegraphics[width=0.4\textwidth]{graphics/simulated-iv-curves.png}
 	\caption{Plot of Shockley first order model for an n-channel MOSFET}
 	\label{fig:nmos-shockley-first-order}
 \end{figure}
 
-We then used a simulation tool that takes into account the non-ideal effects of MOSFETs to provide a more accurate plot of the relationship between input voltages and current. First, an NMOS was placed in the schematic, along with some voltage sources with variable volages. It is important that the voltages be variable, so a parametric test may be run. The final schematic is seen in figure \ref{fig:nmos-iv-schematic}.
+We then used a simulation tool that takes into account the non-ideal effects of MOSFETs to provide a more accurate plot of the relationship between input voltages and current. First, an NMOS was placed in the schematic, along with some voltage sources with variable voltages. It is important that the voltages be variable, so a parametric test may be run. The final schematic is seen in figure \ref{fig:nmos-iv-schematic}.
 
-\begin{figure}[H]
+\begin{figure}[h]
 	\center\includegraphics[width=0.4\textwidth]{graphics/nmos-iv-schematic.png}
 	\caption{NMOS parametric test schematic}
 	\label{fig:nmos-iv-schematic}
 \end{figure}
 
+For the simulation, we set up our output to be the current at the positive terminal of the voltage source V2. We ran a DC sweep simulation of $V_{ds}$, while parametrically stepping through values of $V_{gs}$. The resulting plot is seen in figure \ref{fig:nmos-simulation-results}.
+
+\begin{figure}[h]
+	\center\includegraphics[width=0.4\textwidth]{graphics/iv-curves.png}
+	\caption{Simulated relationship between input voltage and NMOS current}
+	\label{fig:nmos-simulation-results}
+\end{figure}
+
+There is clearly some resemblance between the Shockley model plot and the simulated results. One important difference is that while the curves flatten out completely in the Shockley model, the traces in the simulated NMOS continue to increase well into the saturation region.
+
+
+\section{PMOS Characteristics}
+While the source of an NMOS is tied to ground, the source of a PMOS is tied to power. 
+
+\begin{aside}{Voltage Naming Conventions}
+	The 'D' in $V_{DD}$ actually stands for "drain" despite connecting to the source of the PMOS. Furthermore, the 'S' in $V_{SS}$ does connect to the source pin of the NMOS. This naming convention dates back to a time when BJT logic was the norm. Specifically, NPN BJT logic. With NPNs, the collector is at the most positive voltage, hence the name $V_{CC}$ corresponding to power. When FET logic became popular, the naming scheme remained the same, but with drains and sources in place of collectors and emitters. Hence, $V_{DD}$ became the name for power, and $V_{SS}$ became the name for ground\cite{VddNaming}.
+\end{aside}
+
+PMOS transistors behave the same as NMOS, with the signs of all the voltages and currents flipped\cite{VLSICircuitsSystems}. It is also important to note that by changing the signs, the inequalities flip as well, meaning that quantities that must be greater than others for an NMOS are now required to be less, and vice versa. Therefore, the Shockley model for the current through a PMOS is
+\begin{equation}
+	I_{ds} = \begin{cases}
+		0 & V_{gs} > V_t \\
+		-\beta \left(V_{gs} - V_t - \frac{V_{ds}}{2}\right) V_{ds} & V_{ds} > V_{dsat} \\
+		-\frac{\beta}{2}\left(V_{gs} - V_t\right)^2 & V_{ds} < V_{dsat}
+	\end{cases}.
+	\label{eqn:pmos-shockley-first-order}
+\end{equation}
+
+With this knowledge, we modified our Python script to model a PMOS. The Shockley model plot seen in figure \ref{fig:pmos-shockley} has the same shape as the plot for the NMOS, but rotated $180^\circ$ about the origin. 
+
+\begin{figure}[h]
+	\center\includegraphics[width=0.4\textwidth]{graphics/pmos-shockley-model.png}
+	\caption{Plot of Shockley first order model for a p-channel MOSFET}
+	\label{fig:pmos-shockley}
+\end{figure}
+
+Again, we compared the Shockley model against simulation results. In our schematic, the voltage source for $V_{gs}$ was tied to power instead of ground, and the voltage source for $V_{ds}$ was rotated $180^\circ$. Furthermore, the body pin of the PMOS was tied to power instead of ground. All of these changes are seen in the PMOS test schematic seen in figure \ref{fig:pmos-iv-schematic}.
+
+\begin{figure}[h]
+	\center\includegraphics[width=0.4\textwidth]{graphics/pmos-iv-schematic.png}
+	\caption{PMOS parametric test schematic}
+	\label{fig:pmos-iv-schematic}
+\end{figure}
+
+Finally, we ran the simulation, this time measuring the current at the drain pin of the PMOS. We swept $V_{ds}$ from -2V to 0V with a step size of 0.1V, and parametrically swept $V_{gs}$ from -2.5V to 0V with a step size of 0.25V. The result was a similar plot to the NMOS simulation, again, rotated $180^\circ$ about the origin, as seen in figure \ref{fig:pmos-iv-simulation}. Another difference between the NMOS and PMOS simulations is the actual values of the current. While the shapes are similar, the PMOS current is less than the NMOS current for the same voltage inputs.
+
+\begin{figure}[h]
+	\center\includegraphics[width=0.4\textwidth]{graphics/pmos-iv-2.png}
+	\caption{Simulated relationship between input voltages and PMOS current}
+	\label{fig:pmos-iv-simulation}
+\end{figure}
+
 \section{The Noise Margin}
-The noise margin is the amount of noise that a CMOS circuit can withstand without compromising the operation of the circuit\cite{VLSI_System_Design}. This region is necessary to create a buffer that prevents small amounts of noise from switching the logic. There are two noise margins: noise margin high (NM\textsubscript{H}) and noise margin low (NM\textsubscript{L}). 
+The noise margin is the amount of noise that a CMOS circuit can withstand without compromising the operation of the circuit\cite{VLSISystemDesign}. This region is necessary to create a buffer that prevents small amounts of noise from switching the logic. There are two noise margins: noise margin high (NM\textsubscript{H}) and noise margin low (NM\textsubscript{L}). 
 
 The two noise margins are defined in terms of four key voltages on the voltage transfer curve (VTC) seen in figure \ref{fig:inv_vtc}: $V_\text{IL}$, $V_\text{IH}$, $V_\text{OL}$, and $V_\text{OH}$. $V_\text{IL}$ is defined as the lower input voltage where the slope of the VTC is -1, and $V_\text{IH}$ is defined as the upper input voltage meeting the same requirement. $V_\text{OL}$ is defined as the output voltage when the input voltage is equal to $V_\text{IH}$, and similarly, $V_\text{OH}$ is defined as the output voltage when the input voltage is equal to $V_\text{IL}$.
 
-\begin{figure}[H]
+Practically speaking, when the input voltage is between $V_{OL}$ and $V_{IL}$ it is interpreted as logic low, and when the input voltage is between $V_{IH}$ and $V_{OH}$ it is interpreted as logic high. The region between $V_{IL}$ and $V_{IH}$ is the "undefined region", where the logic state is unclear \cite{VLSISystemDesign}.
+
+\begin{figure}[h]
 	\center
 	\includegraphics[width=0.4\textwidth]{graphics/inverter-noise-margin.png}
 	\caption{The VTC and its derivative for a CMOS inverter with $w_p=240$[nm] and $w_n=120$[nm]}
 	\label{fig:inv_vtc}.
 \end{figure}
 
+We pulled the VTC into a calculator tool, and used the definitions for the different voltages associated with the noise margin. Evaluating the expressions produced the values seen in table \ref{tbl:vtc-voltages}.
+
 \begin{table}[H]
 \center
 \caption{Important VTC voltages}
 \begin{tabular}{c | c}
-	$V_\text{IL}$ & 2.357 \\
+	$V_\text{IL}$ & 2.357[V] \\
 	\hline
-	$V_\text{IH}$ & 3.531 \\
+	$V_\text{IH}$ & 3.531[V] \\
 	\hline
-	$V_\text{OL}$ & 0.683 \\
+	$V_\text{OL}$ & 0.683[V] \\
 	\hline
-	$V_\text{OH}$ & 4.118 \\
+	$V_\text{OH}$ & 4.118[V] \\
 \end{tabular}
+\label{tbl:vtc-voltages}
 \end{table}
 
 With these voltages now defined, the noise margin high was calculated using
@@ -111,9 +185,34 @@ and noise margin low was calculated with
 \begin{equation}
 	\text{NM}_\text{L} = V_\text{IL} - V_\text{OL}.
 \end{equation}
+Therefore, $\text{NM}_\text{H} = 0.587$[V] and $\text{NM}_\text{L} = 1.674$[V]. Any voltage existing within the high noise margin would be interpreted as a logic 1 for this inverter, and any voltage existing within the low noise margin would be interpreted as a logic 0. By definition, the larger the noise margin, the more noise the signal can handle without affecting the logic state. Therefore, this inverter can handle more noise when in the logic low state than in the logic high state. 
 
-\section{Discussion}
+The noise margin is not the same for all inverters, however. To see how the noise margin changes when the MOSFETs used are sized differently, a parametric test was conducted. The width of the NMOS was held constant at 120[nm], but the width of the PMOS was parametrically varied from 120[nm] to 360[nm] with 5 steps in a logarithmic sweep. The resulting VTC is seen in figure \ref{fig:inv-parametric-vtc}. This test produced six traces, where the inverter switched at different input voltages, depending on the width of the PMOS.
+
+\begin{figure}[h]
+	\center\includegraphics[width=0.4\textwidth]{graphics/inv-parametric-nm-1.png}
+	\caption{Inverter VTC for different widths of the PMOS}
+	\label{fig:inv-parametric-vtc}
+\end{figure}
+
+Again, the VTC was pulled into a calculator tool to determine the derivative, and ultimately, the four voltages associated with the noise margin. Since there were six traces, the result was six derivatives, and a range of values for $V_{OH}$, $V_{IH}$, $V_{OL}$, and $V_{IL}$. The four important voltages were plotted as a function of the width of the PMOS $w_p$, seen in figure \ref{fig:inv-parametric-nm-voltages}.
+
+\begin{figure}[h]
+	\center\includegraphics[width=0.4\textwidth]{graphics/inv-parametric-nm-4.png}
+	\caption{$V_{OH}$ (green), $V_{IH}$ (yellow), $V_{OL}$ (cyan), and $V_{IL}$ (red) as a function of $w_p$.}
+	\label{fig:inv-parametric-nm-voltages}
+\end{figure}
+
+Finally, the noise margins were calculated at each $w_p$ using the four already calculated voltages, and the results were plotted in figure \ref{fig:inv-parametric-nm}. The high noise margin shrinks as $w_p$ increases, while the low noise margin grows. However, the sum of $\text{NM}_\text{L}$ and $\text{NM}_\text{H}$ remains roughly constant, although there is a dip with a minimum where the two noise margins are the same. This means that although the individual noise margins change, the size of the undefined region between logic high and logic low remains about the same. This means that although the individual noise margins change, the size of the undefined region between logic high and logic low remains about the same. This means that although the individual noise margins change, the size of the undefined region between logic high and logic low remains about the same.
+
+\begin{figure}[h]
+	\center\includegraphics[width=0.4\textwidth]{graphics/inv-parametric-nm-3.png}
+	\caption{Resulting $\text{NM}_\text{L}$ (yellow) and $\text{NM}_\text{H}$ (red).}
+	\label{fig:inv-parametric-nm}
+\end{figure}
 
 \section{Conclusion}
+A common theme between analyzing the current through a MOSFET and analyzing the noise margin is the dependence on the physical properties of the MOSFETs. 
 
+\printbibliography
 \end{document}

7th-Semester-Fall-2024/VLSI/labs/lab-1-2/lab-1-2.tex.blg

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+[0] Config.pm:307> INFO - This is Biber 2.19
+[0] Config.pm:310> INFO - Logfile is 'lab-1-2.tex.blg'
+[114] biber:340> INFO - === Tue Nov 12, 2024, 21:03:44
+[239] Utils.pm:410> ERROR - Cannot find 'lab-1-2.tex.bcf'!
+[239] Biber.pm:136> INFO - ERRORS: 1

7th-Semester-Fall-2024/VLSI/labs/lab-1-2/references.bib

@@ -0,0 +1,19 @@
+@online{VLSISystemDesign,
+	title = {Noise Margin},
+	year = 2017,
+	url = {https://www.vlsisystemdesign.com/noise-margin/}
+}
+
+@online{VddNaming,
+	title = {What is the difference between VCC, VDD, VEE, VSS},
+	author = {Olin Lathrop},
+	year = 2011,
+	url = {https://electronics.stackexchange.com/questions/17382/what-is-the-difference-between-v-cc-v-dd-v-ee-v-ss}
+}
+
+@book{VLSICircuitsSystems,
+	title = {CMOS VLSI Design a Circuits and Systems Perspective, Fourth Edition},
+	year = 2011,
+	author = {Neil H. E. Weste, David Money Harris},
+	publisher = {Pearson}
+}