Finished VLSI lab 1&2 report

7th-Semester-Fall-2024/VLSI/labs/lab-1-2/lab-1-2.tex

@@ -67,7 +67,7 @@ In CMOS VLSI design, there are two types of complementary MOSFETs, hence the nam
 We will discuss the exact behavior of the two types of MOSFETs further throughout the following two sections. In the final section, we will explore and discuss the properties and behaviors of a CMOS inverter.
 
 \section{NMOS Characteristics}
-The Shockley first-order model is a good approximation of the relationship between the input voltages and the current through a MOSFET. The model approximates the current through an NMOS $I_{ds}$ is
+The Shockley first-order model is a good approximation of the relationship between the input voltages to and the current through a MOSFET. The model approximates the current through an NMOS $I_{ds}$ as
 \begin{equation}
 	I_{ds} = \begin{cases}
 		0 & V_{gs} < V_t \\
@@ -78,7 +78,7 @@ The Shockley first-order model is a good approximation of the relationship betwe
 \end{equation}
 where $V_{gs}$ is the voltage between the gate and source, $V_t$ is the threshold voltage, $V_{ds}$ is the voltage between the drain and the source, $V_{dsat} = V_{gs} - V_t$, and $\beta$ is a constant based on the physical properties of the MOSFET. 
 
-We parametrically varied $V_{gs}$ and $V_{ds}$ using a Python. Then, we plotted $I_{ds}$ using the model described in equation \ref{eqn:nmos-shockley-first-order}. Seen in figure \ref{fig:nmos-shockley-first-order}, increasing $V_{gs}$ will increase the current. Furthermore, increasing $V_{ds}$ will also increase the current, but only up to a point. After reaching that point, the current does not change with $V_{ds}$.
+We parametrically varied $V_{gs}$ and $V_{ds}$ using a Python script. Then, we plotted $I_{ds}$ using the model described in equation \ref{eqn:nmos-shockley-first-order}. Seen in figure \ref{fig:nmos-shockley-first-order}, increasing $V_{gs}$ will increase the current. Furthermore, increasing $V_{ds}$ will also increase the current, but only up to a point. After reaching that point, the current does not change with $V_{ds}$.
 
 \begin{figure}[h]
 	\center\includegraphics[width=0.4\textwidth]{graphics/simulated-iv-curves.png}
@@ -102,7 +102,7 @@ For the simulation, we set up our output to be the current at the positive termi
 	\label{fig:nmos-simulation-results}
 \end{figure}
 
-There is clearly some resemblance between the Shockley model plot and the simulated results. One important difference is that while the curves flatten out completely in the Shockley model, the traces in the simulated NMOS continue to increase well into the saturation region.
+There is clearly some resemblance between the Shockley model plot and the simulated results. One important difference is that the curves flatten out completely in the Shockley model, while the traces in the simulated NMOS continue to increase well into the saturation region.
 
 
 \section{PMOS Characteristics}
@@ -130,7 +130,7 @@ With this knowledge, we modified our Python script to model a PMOS. The Shockley
 	\label{fig:pmos-shockley}
 \end{figure}
 
-Again, we compared the Shockley model against simulation results. In our schematic, the voltage source for $V_{gs}$ was tied to power instead of ground, and the voltage source for $V_{ds}$ was rotated $180^\circ$. Furthermore, the body pin of the PMOS was tied to power instead of ground. All of these changes are seen in the PMOS test schematic seen in figure \ref{fig:pmos-iv-schematic}.
+Again, we compared the Shockley model against simulation results. In our schematic, the voltage source for $V_{gs}$ was tied to power instead of ground, and the voltage source for $V_{ds}$ was rotated $180^\circ$. Furthermore, the body pin of the PMOS was tied to power instead of ground. All of these changes are reflected in the PMOS test schematic seen in figure \ref{fig:pmos-iv-schematic}.
 
 \begin{figure}[h]
 	\center\includegraphics[width=0.4\textwidth]{graphics/pmos-iv-schematic.png}
@@ -138,7 +138,7 @@ Again, we compared the Shockley model against simulation results. In our schemat
 	\label{fig:pmos-iv-schematic}
 \end{figure}
 
-Finally, we ran the simulation, this time measuring the current at the drain pin of the PMOS. We swept $V_{ds}$ from -2V to 0V with a step size of 0.1V, and parametrically swept $V_{gs}$ from -2.5V to 0V with a step size of 0.25V. The result was a similar plot to the NMOS simulation, again, rotated $180^\circ$ about the origin, as seen in figure \ref{fig:pmos-iv-simulation}. Another difference between the NMOS and PMOS simulations is the actual values of the current. While the shapes are similar, the PMOS current is less than the NMOS current for the same voltage inputs.
+Finally, we ran the simulation, this time measuring the current at the drain pin of the PMOS. We swept $V_{ds}$ from -2V to 0V with a step size of 0.1V, and parametrically swept $V_{gs}$ from -2.5V to 0V with a step size of 0.25V. The result was a similar plot to the NMOS simulation, again, rotated $180^\circ$ about the origin, as seen in figure \ref{fig:pmos-iv-simulation}. Another difference between the NMOS and PMOS simulations is the actual values of the current. While the shapes are similar, the absolute value of the PMOS current is less than the NMOS current for the same absolute value of the voltage inputs.
 
 \begin{figure}[h]
 	\center\includegraphics[width=0.4\textwidth]{graphics/pmos-iv-2.png}
@@ -147,11 +147,11 @@ Finally, we ran the simulation, this time measuring the current at the drain pin
 \end{figure}
 
 \section{The Noise Margin}
-The noise margin is the amount of noise that a CMOS circuit can withstand without compromising the operation of the circuit\cite{VLSISystemDesign}. This region is necessary to create a buffer that prevents small amounts of noise from switching the logic. There are two noise margins: noise margin high (NM\textsubscript{H}) and noise margin low (NM\textsubscript{L}). 
+The noise margin is the amount of noise that a CMOS circuit can withstand without compromising the operation of the circuit\cite{VLSISystemDesign}. This region is necessary to create a buffer that prevents small amounts of noise from affecting the logic state. There are two noise margins: noise margin high (NM\textsubscript{H}) and noise margin low (NM\textsubscript{L}). 
 
 The two noise margins are defined in terms of four key voltages on the voltage transfer curve (VTC) seen in figure \ref{fig:inv_vtc}: $V_\text{IL}$, $V_\text{IH}$, $V_\text{OL}$, and $V_\text{OH}$. $V_\text{IL}$ is defined as the lower input voltage where the slope of the VTC is -1, and $V_\text{IH}$ is defined as the upper input voltage meeting the same requirement. $V_\text{OL}$ is defined as the output voltage when the input voltage is equal to $V_\text{IH}$, and similarly, $V_\text{OH}$ is defined as the output voltage when the input voltage is equal to $V_\text{IL}$.
 
-Practically speaking, when the input voltage is between $V_{OL}$ and $V_{IL}$ it is interpreted as logic low, and when the input voltage is between $V_{IH}$ and $V_{OH}$ it is interpreted as logic high. The region between $V_{IL}$ and $V_{IH}$ is the "undefined region", where the logic state is unclear \cite{VLSISystemDesign}.
+Practically speaking, when the input voltage is between $V_{OL}$ and $V_{IL}$ it is interpreted as logic low, and when the input voltage is between $V_{IH}$ and $V_{OH}$ it is interpreted as logic high. The region between $V_{IL}$ and $V_{IH}$ is the ``undefined region", where the logic state is unclear \cite{VLSISystemDesign}.
 
 \begin{figure}[h]
 	\center
@@ -160,7 +160,7 @@ Practically speaking, when the input voltage is between $V_{OL}$ and $V_{IL}$ it
 	\label{fig:inv_vtc}.
 \end{figure}
 
-We pulled the VTC into a calculator tool, and used the definitions for the different voltages associated with the noise margin. Evaluating the expressions produced the values seen in table \ref{tbl:vtc-voltages}.
+We pulled the VTC into a calculator tool, and implemented the definitions for the different voltages associated with the noise margin. Evaluating the expressions produced the values seen in table \ref{tbl:vtc-voltages}.
 
 \begin{table}[H]
 \center
@@ -203,7 +203,7 @@ Again, the VTC was pulled into a calculator tool to determine the derivative, an
 	\label{fig:inv-parametric-nm-voltages}
 \end{figure}
 
-Finally, the noise margins were calculated at each $w_p$ using the four already calculated voltages, and the results were plotted in figure \ref{fig:inv-parametric-nm}. The high noise margin shrinks as $w_p$ increases, while the low noise margin grows. However, the sum of $\text{NM}_\text{L}$ and $\text{NM}_\text{H}$ remains roughly constant, although there is a dip with a minimum where the two noise margins are the same. This means that although the individual noise margins change, the size of the undefined region between logic high and logic low remains about the same. This means that although the individual noise margins change, the size of the undefined region between logic high and logic low remains about the same. This means that although the individual noise margins change, the size of the undefined region between logic high and logic low remains about the same.
+Finally, the noise margins were calculated at each $w_p$ using the four already calculated voltages, and the results were plotted in figure \ref{fig:inv-parametric-nm}. The high noise margin shrinks as $w_p$ increases, while the low noise margin grows. However, the sum of $\text{NM}_\text{L}$ and $\text{NM}_\text{H}$ remains roughly constant, although there is a dip with a minimum where the two noise margins are the same. This means that although the individual noise margins change, the size of the undefined region between logic high and logic low remains about the same.
 
 \begin{figure}[h]
 	\center\includegraphics[width=0.4\textwidth]{graphics/inv-parametric-nm-3.png}
@@ -212,7 +212,8 @@ Finally, the noise margins were calculated at each $w_p$ using the four already
 \end{figure}
 
 \section{Conclusion}
-A common theme between analyzing the current through a MOSFET and analyzing the noise margin is the dependence on the physical properties of the MOSFETs. 
+A common theme between analyzing the current through a MOSFET and analyzing the noise margin is the dependence on the physical properties of the MOSFETs. The Shockley model describes the effect of the physical properties by packaging them nicely into the $\beta$ term. However, the Shockley model does not take into account any non-ideal effects, which are also based on physical properties of the device.
 
+Going forward, it will be important to fully understand how physical properties affect the behavior of individual MOSFETs as well as entire circuits. In doing so, designs may be fine-tuned to increase speed and minimize losses.
 \printbibliography
 \end{document}