End sem 7; week 2 winter session 2025
BIN
7th-Semester-Fall-2024/ECOMMS/final-project/antenna-setup.jpg
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7th-Semester-Fall-2024/ECOMMS/final-project/antenna-setup.png
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7th-Semester-Fall-2024/ECOMMS/final-project/bfm_demod.py
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import numpy as np
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import scipy as sp
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import sounddevice as sd
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from threading import Thread
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import time
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import queue
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import matplotlib.animation as anim
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import matplotlib.pyplot as plt
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from rtlsdr import RtlSdr
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import asyncio
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import dsp
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class BfmDemod:
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def __init__(self, sdr:RtlSdr, stream:sd.OutputStream, audio_sample_rate:int=48000, num_samples:int=8192):
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self.sdr = sdr
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self.stream = stream
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self.audio_sample_rate = audio_sample_rate
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self.buffer = queue.Queue(10)
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self.num_samples = num_samples
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self.fig, self.ax = plt.subplots()
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self.duration = self.num_samples/self.sdr.sample_rate
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#lower_extent = self.sdr.center_freq - self.sdr.sample_rate/2
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#upper_extent = self.sdr.center_freq + self.sdr.sample_rate/2
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#self.fig, self.ax = plt.subplots()
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#self.ax.xlabel = "Frequency [Hz]"
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#self.ax.ylabel = "Amplitude [dB]"
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#self.ax.set_xlim(left=lower_extent, right=upper_extent)
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# Plot the spectrum of the incoming samples
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def _spectrum_update(self, frame):
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self.ax.clear()
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if self.buffer is not None:
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spectrum = np.abs(sp.fft.fftshift(sp.fft.fft(self.buffer)))**2
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spectrum_db = dsp.db(spectrum)
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self.ax.plot(spectrum_db)
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return self.ax,
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# Begin reading and demodulation
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async def start(self):
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self.stream.start()
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plt.ion()
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self.scatter = self.ax.scatter([], [])
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plt.show()
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async for samples in self.sdr.stream(self.num_samples):
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message = dsp.quad_demod(samples)
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message = dsp.lowpass(message, 16E3, self.sdr.sample_rate)
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message /= np.max(np.abs(message))
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time = len(message)/self.sdr.sample_rate
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num_samples = int(time*self.audio_sample_rate)
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message = sp.signal.resample(message, num_samples)
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message = message.astype(np.float32)
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#self.stream.write(message)
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spectrum = np.abs(sp.fft.fftshift(sp.fft.fft(samples)))**2
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spectrum_db = dsp.db(spectrum)
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self.ax.clear()
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self.ax.plot(spectrum_db)
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self.ax.relim()
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self.ax.autoscale_view()
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self.fig.canvas.draw()
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self.fig.canvas.flush_events()
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await sdr.stop()
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def stop(self):
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self.sdr.cancel_read_async()
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self.reader.join()
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self.stream.stop()
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37
7th-Semester-Fall-2024/ECOMMS/final-project/dsp.py
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import scipy as sp
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import numpy as np
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def chunk_samples(samples, num_rows):
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return samples.reshape((samples.shape[0]//num_rows, num_rows))
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def db(x):
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return 10*np.log10(x)
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def quad_demod(samples):
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return 0.5*np.angle(samples[:-1] * np.conj(samples[1:]))
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def lowpass(data, f_cutoff, f_s):
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nyq = 0.5*f_s
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normal_cutoff = f_cutoff/nyq
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b, a = sp.signal.butter(2, normal_cutoff, btype="low", analog=False)
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y = sp.signal.lfilter(b, a, data)
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return y
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def sdr_bandpass(data, f_pass, f_cutoff, extent_MHz):
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lower_extent = extent_MHz[0]*1E6
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upper_extent = extent_MHz[1]*1E6
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extent_range = upper_extent - lower_extent
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normal_pass = (f_pass - lower_extent)/extent_range
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normal_cutoff = (f_cutoff - lower_extent)/extent_range
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b, a = sp.signal.butter(2, (normal_pass, normal_cutoff), btype="bandpass", analog=False)
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y = sp.signal.lfilter(b, a, data)
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return y
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BIN
7th-Semester-Fall-2024/ECOMMS/final-project/fm.wav
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58
7th-Semester-Fall-2024/ECOMMS/final-project/gfsk_demod.py
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import numpy as np
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import scipy as sp
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from threading import Thread
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import time
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import queue
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import matplotlib.animation as animation
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import matplotlib.pyplot as plt
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from rtlsdr import RtlSdr
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import dsp
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class GFSKDemod:
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def __init__(self, sdr:RtlSdr, baud_rate:int=9600, num_samples:int=512):
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self.sdr = sdr
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self.baud_rate = baud_rate
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self.num_samples = num_samples
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self.fig, self.ax = plt.subplots()
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self.duration = self.num_samples/self.sdr.sample_rate
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# Demodulate an update the sound buffer
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def _demod(self, samples):
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message = dsp.quad_demod(samples)
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message = dsp.lowpass(message, 16E3, self.sdr.sample_rate)
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#message /= np.max(np.abs(message))
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#message = message.astype(np.float32)
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time = len(message)*self.sdr.sample_rate
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t = np.linspace(0,time,len(message))
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return t, message
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# Begin reading and demodulation
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async def start(self):
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plt.ion()
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plt.show()
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async for samples in self.sdr.stream(self.num_samples):
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self.ax.clear()
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t, message = self._demod(samples)
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#num_samples = int(len(message)*self.resample_rate/self.sdr.sample_rate)
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#message = sp.signal.resample(message, num_samples)
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#t = np.linspace(0,1,len(message))*t[:-1]
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#self.ax.plot(t,message)
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#spectrum = np.abs(sp.fft.fftshift(sp.fft.fft(samples)))**2
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#spectrum_db = dsp.db(spectrum)
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#self.ax.plot(spectrum_db)
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self.fig.canvas.draw()
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self.fig.canvas.flush_events()
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def stop(self):
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self.sdr.cancel_read_async()
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20
7th-Semester-Fall-2024/ECOMMS/final-project/sd_test.py
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import numpy as np
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import sounddevice as sd
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import scipy as sp
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from scipy.io import wavfile
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import matplotlib.pyplot as plt
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sample_rate, wav_data = wavfile.read("fm.wav")
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time = len(wav_data)/sample_rate
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new_sample_rate = 48E3
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num_samples = int(time*new_sample_rate)
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plt.subplot(211)
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plt.plot(wav_data)
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wav_data = sp.signal.resample(wav_data, num_samples)
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plt.subplot(212)
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plt.plot(wav_data)
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plt.show()
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sd.play(wav_data, samplerate=new_sample_rate)
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sd.wait()
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from rtlsdr import RtlSdr
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#from rtlsdr.rtlsdrtcp.client import RtlSdrTcpClient
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import numpy as np
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import matplotlib.pyplot as plt
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import scipy as sp
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import asyncio
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import asyncio
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from rtlsdr import RtlSdr
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from bfm_demod import BfmDemod
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from gfsk_demod import GFSKDemod
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import sounddevice as sd
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import numpy as np
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async def streaming():
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def main():
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#sdr = RtlSdrTcpClient(hostname='localhost', port=12345)
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sdr = RtlSdr()
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sdr = RtlSdr()
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async for samples in sdr.stream():
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sdr.set_sample_rate(2.048E6)
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sdr.set_center_freq(434.55E6)
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sdr.set_freq_correction(60)
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sdr.set_gain("auto")
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stream = sd.OutputStream(samplerate=48E3, dtype=np.float32, channels=1)
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sink = GFSKDemod(sdr=sdr)
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#sink = BfmDemod(sdr=sdr, stream=stream)
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loop = asyncio.get_event_loop()
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loop.run_until_complete(sink.start())
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await sdr.stop()
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sdr.close()
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sdr.close()
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if __name__ == "__main__":
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main()
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27
7th-Semester-Fall-2024/ECOMMS/final-project/spectrum.py
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import numpy as np
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import matplotlib.pyplot as plt
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import scipy as sp
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from rtlsdr import RtlSdr
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import asyncio
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import dsp
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class Spectrum(Display):
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def __init__(self):
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pass
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def put(self, samples):
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self.buffer.put(samples)
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def update(self):
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samples = self.buffer.get()
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spectrum = np.abs(sp.fft.fftshift(sp.fft.fft(samples)))**2
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spectrum_db = dsp.db(spectrum)
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self.ax.clear()
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self.ax.plot(spectrum_db)
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self.ax.relim()
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self.ax.autoscale_view()
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self.fig.canvas.draw()
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self.fig.canvas.flush_events()
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# Homework 4 - Aidan Sharpe
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## Problem 1
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A multilevel digital communication system sends one of 16 possible levels over the channel every 0.8[ms].
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### a
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What is the number of bits corresponding to each level? Or what is the number of bits per symbol?
|
||||||
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|
||||||
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16 levels $= \log_2(16) = 4$ bits per symbol.
|
||||||
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|
||||||
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### b
|
||||||
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What is the baud rate?
|
||||||
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|
||||||
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1 symbol per 0.8[ms] $= \frac{1}{0.8 \times 10^{-3}} = 1250$ symbols per second.
|
||||||
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|
||||||
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### c
|
||||||
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What is the bit rate?
|
||||||
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|
||||||
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4 bits per symbol at 1250 baud is 5000[bps].
|
||||||
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|
||||||
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## Problem 2
|
||||||
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The input to a differential coding signal is 10110010. Begin with reference digit 1. What is the encoded sequence?
|
||||||
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|
||||||
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Apply XOR operation to each element, diagonally down and left, and store the result below.
|
||||||
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|
||||||
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| | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 |
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|---|---|---|---|---|---|---|---|---|
|
||||||
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| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 |
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BIN
7th-Semester-Fall-2024/ECOMMS/homework/homework-4/homework-4.pdf
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# Homework 5 - Aidan Sharpe
|
||||||
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|
||||||
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## Problem 1
|
||||||
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In a binary communication system, let the receiver test statistic of the received signal be $r_0$. The received signal consists of a polar digital signal plus noise. The polar signal has values $s_{01}=A$ and $s_{02}=-A$. Assume that the noise has a Laplacian distribution:
|
||||||
|
$$f(n_0) = \frac{1}{\sqrt{2} \sigma_0} e^{-\sqrt{2}|n_0|/\sigma_0}$$
|
||||||
|
where $\sigma_0$ is the RMS value of the noise, $f(n_0)$ is the probability density function (PDF), and $n_0$ is the signal. In the case of a PDF of $s_{01}$ and $s_{02}$, replace $n_0$ by $r_0-A$ and $r_0+A$. The shape of the PDF for $s_{01}$ and $s_{02}$ is the same. Find the probability of error $P_e$ as a function of $A/\sigma_0$ for the case of equally likely signaling and $V_T$ having the optimum value.
|
||||||
|
|
||||||
|
|
||||||
|
Given the two PDFs corresponding to $s_1$ and $s_2$, the probability of a bit error is the same as the area of the intersection of the two PDFs, as seen in figure \ref{error_pdfs}.
|
||||||
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|
||||||
|

|
||||||
|
|
||||||
|
The curve traced out by this area is
|
||||||
|
$$p(r_0) = \frac{1}{2}\left[f(r_0 | s_1) + f(r_0 | s_2) - \|f(r_0 | s_1) - f(r_0 | s_2) \|\right]$$
|
||||||
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|
||||||
|
to find the area under the curve (the probability of a bit error $P_e$), we integrate $p(r_0)$ for all values of $r_0$. Since $f(r_0 | s_1)$ and $f(r_0 | s_2)$ are PDFs, the area under each must be unity. Therefore, distributing the $\frac{1}{2}$ term, we are left with:
|
||||||
|
$$P_e = 1 - \frac{1}{2} \int\limits_{-\infty}^\infty \left|f(r_0 | s_1) - f(r_0 | s_2)\right| dr_0$$
|
||||||
|
|
||||||
|
Finally, we expand and simplify the integral to:
|
||||||
|
|
||||||
|
$$P_e = 1 - \frac{\sqrt{2}}{4\sigma_0} \int\limits_{-\infty}^\infty \left|e^{-\sqrt{2} |r_0-A| /\sigma_0} - e^{-\sqrt{2} |r_0 + A|/\sigma_0}\right| dr_0$$
|
||||||
|
|
||||||
|
After evaluating the intergral, we find that $P_e = e^{-\sqrt{2}A/\sigma_0}$.
|
||||||
|
|
||||||
|
|
||||||
|
## Problem 2
|
||||||
|
A digital signal with white Gaussian noise is received by a receiver with a matched filter. The signal is a unipolar non-return to zero signal with $s_{01}=1$[V] and $s_{02}=0$[V]. The bit rate is 1 Mbps. The power spectral density of the noise is $N_0/2=10^{-8}$[W/Hz]. What is the probability of error $P_e$? Assume the white Gaussian noise is thermal noise.
|
||||||
|
|
||||||
|
For a unipolar signal received by a receiver with a matched filter, the probability of error is given by:
|
||||||
|
$$P_e = Q\left(\sqrt{\frac{A^2 T}{4 N_0}}\right)$$
|
||||||
|
where $A = 1 - 0 = 1$ is the amplitude and $T= 1[\mu$s]. Therefore, $P_e = 2.03 \times 10^{-4}$.
|
BIN
7th-Semester-Fall-2024/ECOMMS/homework/homework-5/homework-5.pdf
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BIN
7th-Semester-Fall-2024/ECOMMS/homework/homework-5/prob-err.png
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|
import numpy as np
|
||||||
|
import matplotlib.pyplot as plt
|
||||||
|
import scipy as sp
|
||||||
|
|
||||||
|
def laplacian_distribution(n_0, std_dev):
|
||||||
|
return np.exp(-np.sqrt(2)*np.abs(n_0)/std_dev) / (np.sqrt(2)*std_dev)
|
||||||
|
|
||||||
|
def main():
|
||||||
|
r_0 = np.linspace(-5,5,1000)
|
||||||
|
A = 1
|
||||||
|
std_dev = 1
|
||||||
|
|
||||||
|
low_dist = laplacian_distribution(r_0 - A, std_dev)
|
||||||
|
up_dist = laplacian_distribution(r_0 + A, std_dev)
|
||||||
|
|
||||||
|
plt.plot(r_0, low_dist, label="$s_1$")
|
||||||
|
plt.plot(r_0, up_dist, label="$s_2$")
|
||||||
|
|
||||||
|
P_error = (up_dist + low_dist - np.abs(up_dist-low_dist))/2
|
||||||
|
plt.fill_between(r_0, P_error, color=(0,0,0,0), hatch="//", edgecolor='k', label="$P_e$")
|
||||||
|
|
||||||
|
plt.legend()
|
||||||
|
|
||||||
|
plt.savefig("Probability of error")
|
||||||
|
|
||||||
|
plt.show()
|
||||||
|
|
||||||
|
|
||||||
|
if __name__ == "__main__":
|
||||||
|
main()
|
BIN
7th-Semester-Fall-2024/ECOMMS/labs/lab2/Ecomms_Lab_2.pdf
Normal file
@ -2,7 +2,7 @@ import numpy as np
|
|||||||
import matplotlib.pyplot as plt
|
import matplotlib.pyplot as plt
|
||||||
import scipy as sp
|
import scipy as sp
|
||||||
|
|
||||||
def add_noise_snr_db(s, SNR):
|
def add_noise(s, SNR):
|
||||||
var_s = np.cov(s)
|
var_s = np.cov(s)
|
||||||
var_noise = var_s/(10**(SNR/10))
|
var_noise = var_s/(10**(SNR/10))
|
||||||
noise = var_noise**0.5 * np.random.randn(len(s))
|
noise = var_noise**0.5 * np.random.randn(len(s))
|
||||||
@ -51,14 +51,6 @@ def main():
|
|||||||
s_am = dsb_am(m, f_c, t)
|
s_am = dsb_am(m, f_c, t)
|
||||||
s_sc = dsb_sc(m, f_c, t)
|
s_sc = dsb_sc(m, f_c, t)
|
||||||
|
|
||||||
plt.subplot(311)
|
|
||||||
plt.plot(t, m, label="Message Signal")
|
|
||||||
plt.subplot(312)
|
|
||||||
plt.plot(t, s_am, label="DSB-AM Modulated Signal")
|
|
||||||
plt.subplot(313)
|
|
||||||
plt.plot(t, s_sc, label="DSB-SC Modulated Signal")
|
|
||||||
plt.show()
|
|
||||||
|
|
||||||
m_am_demod = product_demod(s_am, f_m, f_c, f_s, t)
|
m_am_demod = product_demod(s_am, f_m, f_c, f_s, t)
|
||||||
m_sc_demod = product_demod(s_sc, f_m, f_c, f_s, t)
|
m_sc_demod = product_demod(s_sc, f_m, f_c, f_s, t)
|
||||||
|
|
||||||
@ -66,14 +58,17 @@ def main():
|
|||||||
plt.plot(t, m_am_demod, label="Demodulated DSB-AM Signal")
|
plt.plot(t, m_am_demod, label="Demodulated DSB-AM Signal")
|
||||||
plt.plot(t, m_sc_demod, label="Demodulated DSB-SC Signal")
|
plt.plot(t, m_sc_demod, label="Demodulated DSB-SC Signal")
|
||||||
plt.legend(loc="upper right")
|
plt.legend(loc="upper right")
|
||||||
|
plt.savefig("demodulation-clean.png")
|
||||||
plt.show()
|
plt.show()
|
||||||
|
|
||||||
m_am_noisy_demod = product_demod(add_noise_snr_db(s_am, 3), f_m, f_c, f_s, t)
|
m_am_noisy_demod = product_demod(add_noise_snr_db(s_am, 3), f_m, f_c, f_s, t)
|
||||||
m_sc_noisy_demod = product_demod(add_noise_snr_db(s_sc, 3), f_m, f_c, f_s, t)
|
m_sc_noisy_demod = product_demod(add_noise_snr_db(s_sc, 3), f_m, f_c, f_s, t)
|
||||||
|
|
||||||
plt.plot(t, m)
|
plt.plot(t, m, label="Original Message Signal")
|
||||||
plt.plot(t, m_am_noisy_demod)
|
plt.plot(t, m_am_noisy_demod, label="Demodulated DSB-AM Signal With Noise")
|
||||||
plt.plot(t, m_sc_noisy_demod)
|
plt.plot(t, m_sc_noisy_demod, label="Demodulated DSB-SC Signal With Noise")
|
||||||
|
plt.legend(loc="upper right")
|
||||||
|
plt.savefig("demodulation-noisy.png")
|
||||||
plt.show()
|
plt.show()
|
||||||
|
|
||||||
if __name__ == "__main__":
|
if __name__ == "__main__":
|
||||||
|
BIN
7th-Semester-Fall-2024/ECOMMS/labs/lab2/demodulation-clean.png
Normal file
After Width: | Height: | Size: 71 KiB |
BIN
7th-Semester-Fall-2024/ECOMMS/labs/lab2/demodulation-noisy.png
Normal file
After Width: | Height: | Size: 75 KiB |
BIN
7th-Semester-Fall-2024/ECOMMS/labs/lab3/Ecomms_Lab_3.pdf
Normal file
BIN
7th-Semester-Fall-2024/ECOMMS/labs/lab3/fm-signal.png
Normal file
After Width: | Height: | Size: 92 KiB |
140
7th-Semester-Fall-2024/ECOMMS/labs/lab3/lab-3.py
Normal file
@ -0,0 +1,140 @@
|
|||||||
|
import numpy as np
|
||||||
|
import matplotlib.pyplot as plt
|
||||||
|
import scipy as sp
|
||||||
|
|
||||||
|
def add_noise(s, SNR):
|
||||||
|
var_s = np.cov(s)
|
||||||
|
var_noise = var_s/(10**(SNR/10))
|
||||||
|
noise = var_noise**0.5 * np.random.randn(len(s))
|
||||||
|
return s + noise
|
||||||
|
|
||||||
|
def add_noise_db(s, noise_db):
|
||||||
|
var_noise = 10**(noise_db/10)
|
||||||
|
noise = var_noise**0.5 * np.random.randn(len(s))
|
||||||
|
return s + noise
|
||||||
|
|
||||||
|
|
||||||
|
def lowpass(data, f_cutoff, f_s):
|
||||||
|
nyq = 0.5*f_s
|
||||||
|
normal_cutoff = f_cutoff/nyq
|
||||||
|
b, a = sp.signal.butter(2, normal_cutoff, btype="low", analog=False)
|
||||||
|
y = sp.signal.lfilter(b, a, data)
|
||||||
|
return y
|
||||||
|
|
||||||
|
def bandpass(data, f_pass, f_cutoff, f_s):
|
||||||
|
nyq = 0.5*f_s
|
||||||
|
|
||||||
|
normal_pass = f_pass/nyq
|
||||||
|
normal_cutoff = f_cutoff/nyq
|
||||||
|
|
||||||
|
b, a = sp.signal.butter(2, (normal_pass, normal_cutoff), btype="bandpass", analog=False)
|
||||||
|
y = sp.signal.lfilter(b, a, data)
|
||||||
|
return y
|
||||||
|
|
||||||
|
def fm(m, f_c, beta_f, t):
|
||||||
|
omega_c = 2*np.pi*f_c
|
||||||
|
return np.cos(omega_c*t + beta_f*m)
|
||||||
|
|
||||||
|
def product_demod(s, f_baseband, f_c, f_s, t):
|
||||||
|
omega_c = 2*np.pi*f_c
|
||||||
|
mixed = s*np.cos(omega_c*t)
|
||||||
|
return lowpass(mixed, f_baseband, f_s)
|
||||||
|
|
||||||
|
|
||||||
|
def fm_demod(s_fm, f_c, f_s, beta_f, t):
|
||||||
|
diff_t = np.gradient(s_fm, t)
|
||||||
|
envelope = np.abs(sp.signal.hilbert(diff_t))
|
||||||
|
|
||||||
|
omega_c = 2*np.pi*f_c
|
||||||
|
dt = 1/f_s
|
||||||
|
m_demod = np.empty_like(envelope)
|
||||||
|
|
||||||
|
#err1 = dt*(envelope[0] + envelope[1] - 2*omega_c)/beta_f**2
|
||||||
|
#err2 = dt*(dm_dt[0] + dm_dt[1])/beta_f
|
||||||
|
|
||||||
|
for i in range(len(envelope)):
|
||||||
|
m_demod[i] = np.sum((envelope[:i+1] - omega_c)/(beta_f*f_s))
|
||||||
|
|
||||||
|
return m_demod
|
||||||
|
|
||||||
|
def quad_demod(s_fm, bandwidth, f_s, f_c, t):
|
||||||
|
iq = real_to_iq(s_fm, f_c, bandwidth, f_s, t)
|
||||||
|
iq = np.conj(iq)
|
||||||
|
return 0.5*np.angle(iq)
|
||||||
|
|
||||||
|
def real_to_iq(s_fm, f_c, bandwidth, f_s, t):
|
||||||
|
i = lowpass(s_fm * np.cos(2*np.pi*f_c*t), bandwidth, f_s)
|
||||||
|
q = lowpass(s_fm * np.sin(2*np.pi*f_c*t), bandwidth, f_s)
|
||||||
|
return i + 1j*q
|
||||||
|
|
||||||
|
|
||||||
|
def m(t):
|
||||||
|
f_m = 10
|
||||||
|
omega_m = 2*np.pi*f_m
|
||||||
|
return 0.1*np.sin(omega_m*t)
|
||||||
|
|
||||||
|
def dm_dt(t):
|
||||||
|
f_m = 10
|
||||||
|
omega_m = 2*np.pi*f_m
|
||||||
|
return 0.1*omega_m*np.cos(omega_m*t)
|
||||||
|
|
||||||
|
def db(x):
|
||||||
|
return 10*np.log10(x)
|
||||||
|
|
||||||
|
def main():
|
||||||
|
T_s = 0.0001
|
||||||
|
f_s = 1/T_s
|
||||||
|
f_m = 20
|
||||||
|
omega_m = 2*np.pi*f_m
|
||||||
|
|
||||||
|
f_c = 500
|
||||||
|
|
||||||
|
beta_f = 2.40483
|
||||||
|
|
||||||
|
t = np.arange(0,1,T_s)
|
||||||
|
f = np.linspace(-f_s/2, f_s/2, len(t))
|
||||||
|
|
||||||
|
#m = 0.5*(np.sin(omega_m*t) + np.sin(omega_m/2*t))
|
||||||
|
m = np.sin(omega_m*t)
|
||||||
|
s_fm = fm(m, f_c, beta_f, t)
|
||||||
|
|
||||||
|
omega_c = 2*np.pi*f_c
|
||||||
|
|
||||||
|
#plt.plot(t, m, label="Original Message Signal")
|
||||||
|
#plt.plot(t, quad_demod(s_fm, 2*f_m, f_s, f_c, t), label="Demodulated Message")
|
||||||
|
#plt.legend()
|
||||||
|
#plt.savefig("message-signals")
|
||||||
|
#plt.show()
|
||||||
|
|
||||||
|
#plt.plot(t, s_fm, label="Frequency Modulated Message")
|
||||||
|
#plt.legend()
|
||||||
|
#plt.savefig("fm-signal")
|
||||||
|
#plt.show()
|
||||||
|
|
||||||
|
|
||||||
|
spectrum = np.abs(sp.fft.fftshift(sp.fft.fft(s_fm)))**2
|
||||||
|
#spectrum_db = db(spectrum)
|
||||||
|
|
||||||
|
plt.subplot(121)
|
||||||
|
plt.plot(f, spectrum)
|
||||||
|
#plt.vlines(f_c, -250, 100, color='r')
|
||||||
|
plt.xlim(0,2*f_c)
|
||||||
|
plt.title("Null Carrier Spectrum")
|
||||||
|
plt.xlabel("Frequency [Hz]")
|
||||||
|
|
||||||
|
beta_f = 5
|
||||||
|
m = np.sin(omega_m*t)
|
||||||
|
s_fm = fm(m, f_c, beta_f, t)
|
||||||
|
spectrum = np.abs(sp.fft.fftshift(sp.fft.fft(s_fm)))**2
|
||||||
|
|
||||||
|
plt.subplot(122)
|
||||||
|
plt.title("Non-null Carrier Spectrum")
|
||||||
|
plt.plot(f, spectrum)
|
||||||
|
plt.xlim(0,2*f_c)
|
||||||
|
plt.xlabel("Frequency [Hz]")
|
||||||
|
plt.savefig("null-carrier-comp")
|
||||||
|
|
||||||
|
plt.show()
|
||||||
|
|
||||||
|
if __name__ == "__main__":
|
||||||
|
main()
|
BIN
7th-Semester-Fall-2024/ECOMMS/labs/lab3/lab-3.py.pdf
Normal file
BIN
7th-Semester-Fall-2024/ECOMMS/labs/lab3/message-signals.png
Normal file
After Width: | Height: | Size: 65 KiB |
BIN
7th-Semester-Fall-2024/ECOMMS/labs/lab3/non-null-carrier.png
Normal file
After Width: | Height: | Size: 14 KiB |
BIN
7th-Semester-Fall-2024/ECOMMS/labs/lab3/null-carrier-comp.png
Normal file
After Width: | Height: | Size: 23 KiB |
BIN
7th-Semester-Fall-2024/ECOMMS/labs/lab3/null-carrier.png
Normal file
After Width: | Height: | Size: 9.9 KiB |
4800
7th-Semester-Fall-2024/Ethical-Hacking/Top4800-WPA-probable-v2.txt
Normal file
@ -0,0 +1,43 @@
|
|||||||
|
# Assignment 5 - Aidan Sharpe
|
||||||
|
|
||||||
|
## Task 1: Setting Up Burp Suite
|
||||||
|
Configure Burp Suite to intercept traffic from your browser and verify the setup.
|
||||||
|
|
||||||
|

|
||||||
|
|
||||||
|
## Task 2: Testing for SQL Injection with Burp Repeater
|
||||||
|
Use Burp Repeater to test for SQL injection vulnerabilities on the DVWA login page.
|
||||||
|
|
||||||
|
|
||||||
|

|
||||||
|
|
||||||
|
## Task 3: Conducting a Brute Force Attack with Burp Intruder
|
||||||
|
Use Burp Intruder to perform a brute force attack on DVWA’s login page.
|
||||||
|
|
||||||
|
We found a list of usernames and passwords online, and loaded them into Burp Suite. We used the cluster bomb attack to go through all possible combinations in the two lists. We also turned redirect to "allow on-site" to make it easier to identify a successful login. The correct credentials had a response length of 4391, while the other credentials had a response length of 1675.
|
||||||
|
|
||||||
|

|
||||||
|
|
||||||
|
## Task 4: Testing for Cross-Site Scripting (XSS)
|
||||||
|
Test for XSS vulnerabilities by injecting JavaScript payloads into input fields.
|
||||||
|
|
||||||
|
We inserted the script `<script>alert('XSS')</script>` into the "What's your name?" field on the "XSS reflected" page. When the "submit" button was pressed, we were greeted with:
|
||||||
|
|
||||||
|

|
||||||
|
|
||||||
|
## Task 5: Analyzing and Reporting Results
|
||||||
|
Analyze the results from your tests and identify potential vulnerabilities in DVWA.
|
||||||
|
|
||||||
|
SQL injection and XSS are both forms of arbitrary code execution. SQL injection poses a threat to the confidentiality of database entries, while the XSS vulnerability allows the execuation of code on client machines.
|
||||||
|
|
||||||
|
The brute force attack allows unauthorized people to login as any user. While it is not an efficient way to gain access, it can be effective against common or default passwords.
|
||||||
|
|
||||||
|
## Task 6: Mitigation Recommendations
|
||||||
|
SQL injection and XSS vulnerabilities can be mitigated via better string handling. They are caused by strings being processed as code when they should be only processed as text. To mitigate these types of attacks, better string input handling should be implemented. There exist many freely available libraries to protect applications from SQL injection and XSS vulnerabilities.
|
||||||
|
|
||||||
|
Brute force attacks, on the other hand, can be mitigated by limiting the number of unsuccessful login attempts. This can be done by applying a timer, or by locking the session.
|
||||||
|
|
||||||
|
## Task 7: Reflection
|
||||||
|
There are a wide array vulnerabilities that can be exploited at the application layer. While these attacks may not provide direct access to internal networks, they can certainly be used as an entry point.
|
||||||
|
|
||||||
|
These types of vulnerabilities also make it clear that the internet was not designed with security in mind, and that extra measures must be put in place to protect web applications from external attacks.
|
After Width: | Height: | Size: 76 KiB |
After Width: | Height: | Size: 154 KiB |
After Width: | Height: | Size: 117 KiB |
After Width: | Height: | Size: 56 KiB |
After Width: | Height: | Size: 127 KiB |
After Width: | Height: | Size: 230 KiB |
After Width: | Height: | Size: 42 KiB |
BIN
7th-Semester-Fall-2024/Ethical-Hacking/output_file-01.cap
Normal file
@ -0,0 +1,5 @@
|
|||||||
|
|
||||||
|
BSSID, First time seen, Last time seen, channel, Speed, Privacy, Cipher, Authentication, Power, # beacons, # IV, LAN IP, ID-length, ESSID, Key
|
||||||
|
|
||||||
|
Station MAC, First time seen, Last time seen, Power, # packets, BSSID, Probed ESSIDs
|
||||||
|
|
|
@ -0,0 +1 @@
|
|||||||
|
Network;NetType;ESSID;BSSID;Info;Channel;Cloaked;Encryption;Decrypted;MaxRate;MaxSeenRate;Beacon;LLC;Data;Crypt;Weak;Total;Carrier;Encoding;FirstTime;LastTime;BestQuality;BestSignal;BestNoise;GPSMinLat;GPSMinLon;GPSMinAlt;GPSMinSpd;GPSMaxLat;GPSMaxLon;GPSMaxAlt;GPSMaxSpd;GPSBestLat;GPSBestLon;GPSBestAlt;DataSize;IPType;IP;
|
|
@ -0,0 +1,6 @@
|
|||||||
|
<?xml version="1.0" encoding="ISO-8859-1"?>
|
||||||
|
<!DOCTYPE detection-run SYSTEM "http://kismetwireless.net/kismet-3.1.0.dtd">
|
||||||
|
|
||||||
|
<detection-run kismet-version="airodump-ng-1.0" start-time="Thu Nov 21 16:54:04 2024">
|
||||||
|
|
||||||
|
</detection-run>
|
@ -0,0 +1 @@
|
|||||||
|
LocalTime, GPSTime, ESSID, BSSID, Power, Security, Latitude, Longitude, Latitude Error, Longitude Error, Type
|
|
BIN
7th-Semester-Fall-2024/Ethical-Hacking/output_file-02.cap
Normal file
@ -0,0 +1,5 @@
|
|||||||
|
|
||||||
|
BSSID, First time seen, Last time seen, channel, Speed, Privacy, Cipher, Authentication, Power, # beacons, # IV, LAN IP, ID-length, ESSID, Key
|
||||||
|
|
||||||
|
Station MAC, First time seen, Last time seen, Power, # packets, BSSID, Probed ESSIDs
|
||||||
|
|
|
@ -0,0 +1 @@
|
|||||||
|
Network;NetType;ESSID;BSSID;Info;Channel;Cloaked;Encryption;Decrypted;MaxRate;MaxSeenRate;Beacon;LLC;Data;Crypt;Weak;Total;Carrier;Encoding;FirstTime;LastTime;BestQuality;BestSignal;BestNoise;GPSMinLat;GPSMinLon;GPSMinAlt;GPSMinSpd;GPSMaxLat;GPSMaxLon;GPSMaxAlt;GPSMaxSpd;GPSBestLat;GPSBestLon;GPSBestAlt;DataSize;IPType;IP;
|
|
@ -0,0 +1,6 @@
|
|||||||
|
<?xml version="1.0" encoding="ISO-8859-1"?>
|
||||||
|
<!DOCTYPE detection-run SYSTEM "http://kismetwireless.net/kismet-3.1.0.dtd">
|
||||||
|
|
||||||
|
<detection-run kismet-version="airodump-ng-1.0" start-time="Thu Nov 21 17:01:00 2024">
|
||||||
|
|
||||||
|
</detection-run>
|
@ -0,0 +1 @@
|
|||||||
|
LocalTime, GPSTime, ESSID, BSSID, Power, Security, Latitude, Longitude, Latitude Error, Longitude Error, Type
|
|
After Width: | Height: | Size: 12 KiB |
@ -0,0 +1,17 @@
|
|||||||
|
# VLSI Homework 12 - Aidan Sharpe
|
||||||
|
|
||||||
|
## Problem 12.5
|
||||||
|
Estimate the minimum delay of a 10:1024 decoder driving an electrical effort of $H=20$.
|
||||||
|
|
||||||
|
A 10:1024 decoder will contain 1024 AND gates. It will have a branching effort of $B=1024/2=512$. Assuming $G\approx1$ for a 10-input AND gate, the path effort will be $F=GBH=40960$. The optimal number of stages will be, assuming the stage effort is $\rho=4$, $\hat{N} = \log_4(40960)=7.66$. We will use 8 stages in our solution, seen below.
|
||||||
|
|
||||||
|

|
||||||
|
|
||||||
|
### Using static CMOS gates
|
||||||
|
For a static CMOS design, $G = (4/3)^4 = 256/81$. Therefore, the actual stage effort is $F = GBH = 32363.5$. The parasitic delay is $P = 12$, so the total delay will be $D=NF^{1/N} + P = 41.3\tau$.
|
||||||
|
|
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### Using footless domino gates
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||||||
|
A footless domino design has $g=1/3$ for inverters and $g=2/3$ for NAND2. Therefore, $G=(1/3)^4(2/3)^4=16/6561$, and $F=GBH=24.97$. The parasitic delay for inverters is $p=2/3$, and $p=1$ for NAND2. Therefore, the path parasitic delay is $P=4 + 8/3 = 20/3$. Finally, the total delay will be $D=NF^{1/n} + P = 18.62\tau$.
|
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## Problem 12.12
|
||||||
|
NAND ROMs will have a higher resistance than a comparable NOR ROM, thereby making them slower.
|
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|
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** Conference Paper **
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** Conference Paper **
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Before submitting the final camera ready copy, remember to:
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uses only Type 1 fonts and that every step in the generation
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process uses the appropriate paper size.
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@ -65,7 +65,7 @@ In this lab, we designed and analyzed several simple CMOS gates. Specifically, w
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\section{Inverter}
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\section{Inverter}
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The first, and simplest gate we created was a CMOS inverter. This device is made from one n-channel MOSFET (NMOS), and one p-channel MOSFET (PMOS). Its schematic is seen in figure \ref{fig:inv-sch}. Looking closely, the width of the NMOS is 120nm and the width of the PMOS is 240nm. This was done to match the resistances of the two devices.
|
The first, and simplest gate we created was a CMOS inverter. This device is made from one n-channel MOSFET (NMOS), and one p-channel MOSFET (PMOS). Its schematic is seen in figure \ref{fig:inv-sch}. Looking closely, the width of the NMOS is 120nm and the width of the PMOS is 240nm. This was done to match the resistances of the two devices.
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The equivalent channel resistance of an NMOS is $R = \frac{R_0}{k}$, and for a PMOS, $R = \frac{2R_0}{k}$ \cite{VLSICircuitsSystems}. The constant $k$ is the ratio of the width of the MOSFET to the width of a unit transistor for that technology. For example, the unit transistor for 45nm is 120nm. Therefore, a PMOS will always have twice the resistance of an NMOS for the same width, and if the resistances are to match, then the PMOS must be twice as wide as the NMOS.
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The equivalent channel resistance of an NMOS is $R_n = \frac{R}{k}$, and for a PMOS, $R_p = \frac{2R}{k}$ \cite{VLSICircuitsSystems}. The constant $k$ is the ratio of the width of the MOSFET to the width of a unit transistor for that technology. For example, the unit transistor for our 45[nm] design library is 120[nm]. Therefore, a PMOS will always have twice the resistance of an NMOS of the same width, and if the resistances are to match, then the PMOS must be twice as wide as the NMOS.
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\label{fig:inverter-io}
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Instead of eyeballing the time, we loaded the outputs of the simulation into a calculator tool to precisely calculate the time. This tool was used to calculate all five delay characteristics. The values of the delay characteristics are seen in table \ref{tbl:inv-delay}. It is important to note that the rise and fall times of the input signal are identical, but as seen in the table, the rise and fall times for the output are different. This effect is quite odd. The total output capacitance is $3C_0$ regardless of whether the output is rising or falling, and we picked our $k$ values such that the resistance was $R_0$ for both the pull-up and pull-down network. Therefore, regardless of the edge, the time constant should be $\tau = 3R_0C_0$. Regardless, we still have a difference between the rising and falling edges. The difference likely comes from an assumption we made. We assumed that the resistance for a PMOS is twice that of an NMOS of the same size, but this is merely an approximation to account for holes having lower mobility than electrons\cite{VLSICircuitsSystems}.
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Instead of eyeballing the time, we loaded the outputs of the simulation into a calculator tool to precisely calculate the time. This tool was used to calculate all five delay characteristics. The values of the delay characteristics are seen in table \ref{tbl:inv-delay}. It is important to note that the rise and fall times of the input signal are identical, but as seen in the table, the rise and fall times for the output are different. This effect is quite odd. The total output capacitance is $3C$ regardless of whether the output is rising or falling, and we picked our $k$ values such that the resistance was $R$ for both the pull-up and pull-down network. Therefore, regardless of the edge, the time constant should be $\tau = 3RC$. Regardless, we still have a difference between the rising and falling edges. The difference likely comes from an assumption we made. We assumed that the resistance for a PMOS is twice that of an NMOS of the same size, but this is merely an approximation to account for holes having lower mobility than electrons\cite{VLSICircuitsSystems}.
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\center
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To ensure that our layout met the design rules imposed by the technology library, we used a design rule checker. Our initial design had some small errors, such as the n-well being too close to the contacts to power, but the design rule checker enabled us to rapidly resolve these issues. We also ran another check to ensure that the connections in the layout matched the connections in the schematic. After adding the proper pins, this check also passed. With both checks completed, our inverter was finished.
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To ensure that our layout met the design rules imposed by the technology library, we used a design rule checker. Our initial design had some small errors, such as the n-well being too close to the contacts to power, but the design rule checker enabled us to rapidly resolve these issues. We also ran another check to ensure that the connections in the layout matched the connections in the schematic. After adding the proper pins, this check also passed. With both checks completed, our inverter was finished.
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\section{Conclusion}
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\section{Transmission Gate}
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The workflow implemented enables the rapid re-use of circuits. This concept is important as it is not feasible to layout every MOSFET and every connection in a larger design. By building up a design from previously designed components, keeping track of the characteristics of each piece along the way, it is much easier to create complex digital circuits.
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A transmission gate is similar in construction to an inverter, consisting of one NMOS and one PMOS. A schematic for a CMOS transmission gate is seen in figure \ref{fig:trans-schematic}. When $C$ is low ($\sim C$ is high), the output $Y$ is the same as the input $A$, and when $C$ is high ($\sim C$ is low), the output $Y$ is floating. The transmission gate works well in this layout because the PMOS passes a "strong one" and the NMOS passes a "strong zero".
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\caption{Transmission gate schematic}
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\label{fig:trans-schematic}
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This process is the essence of VLSI. It is not possible for people to build a CPU with billions of transistors one MOSFET at a time. Very large scale designs are only made possible by slowly building up a subsystem by using repeatable elements, and abstracting away the fine details.
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With only one transmission gate, the output signal quality is very good. One thing to keep in mind, however, is that unlike an inverter, where the output power comes from the rails, with a transmission gate, the output power comes directly from the input. Therefore, any noise present in the input will get passed to the output. With a standard CMOS gate, the output noise does not build from stage to stage.
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\center\includegraphics[width=0.4\textwidth]{graphics/tran-signals.png}
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\caption{Transmission gate timing diagram}
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\label{fig:trans-signals}
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When it comes to the pysical layout of the transmission gate shown in figure \ref{fig:trans-layout}, one thing to keep in mind is that $C$ and $\sim C$ are inaccessible on metal1. Therefore, an additional via---metal1 to metal2---would be required for each of the two control inputs.
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\caption{Transmission gate layout}
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\label{fig:trans-layout}
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\section{NAND Gate}
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The NAND gate is the fastest two input CMOS logic gate. It has an input capacitance of 4C compared to the 5C of a NOR gate. The truth table for a NAND is seen in table \ref{tbl:nand-truth}. The output is low only when all inputs are high.
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\begin{table}[h]
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\center
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\caption{NAND gate truth table}
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\begin{tabular}{c c | c}
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A & B & X\\
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\hline
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0 & 0 & 1\\
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0 & 1 & 1\\
|
||||||
|
1 & 0 & 1\\
|
||||||
|
1 & 1 & 0\\
|
||||||
|
\end{tabular}
|
||||||
|
\label{tbl:nand-truth}
|
||||||
|
\end{table}
|
||||||
|
|
||||||
|
The simplest two-input CMOS NAND gate has a pull-up network with two PMOS's in series and a pull-down network with two NMOS's in parallel, seen in figure \ref{fig:nand-schematic}. To establish the same resistance in both networks, all gates are twice the size of a unit transistor. Since the input capacitance is the sum of all gate capacitances for a given input, and the gate capacitance for both n-channel and p-channel MOSFETs is $kC$, we have a total input capacitance of $2C + 2C = 4C$.
|
||||||
|
|
||||||
|
For our 45[nm] technology package, the unit transistor is 120[nm]. Therfore all transistors will have a width of 240[nm]
|
||||||
|
|
||||||
|
\begin{figure}[h]
|
||||||
|
\center\includegraphics[width=0.4\textwidth]{graphics/nand-schematic.png}
|
||||||
|
\caption{Two-input CMOS NAND gate schematic}
|
||||||
|
\label{fig:nand-schematic}
|
||||||
|
\end{figure}
|
||||||
|
|
||||||
|
\section{Conclusion}
|
||||||
|
The workflow implemented enables the rapid re-use of circuits. This concept is important as it is not feasible to lay out every MOSFET and every connection in a larger design. By building up a design from previously designed components, keeping track of the characteristics of each piece along the way, it is much easier to create complex digital circuits.
|
||||||
|
|
||||||
|
This process is the essence of VLSI. It is not possible for people to build a CPU with millions or billions of transistors one MOSFET at a time. Very large scale designs are only made possible by slowly building up a subsystem by using repeatable elements, and abstracting away the fine details.
|
||||||
|
|
||||||
\printbibliography
|
\printbibliography
|
||||||
\end{document}
|
\end{document}
|
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|
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49
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
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\\\\\hline
|
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|
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|
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|
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\hyphenation{op-tical net-works semi-conduc-tor}% correct bad hyphenation here
|
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|
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|
||||||
|
\font\myfont=cmr12 at 15pt
|
||||||
|
\title{\myfont Applying Simple CMOS Gates}
|
||||||
|
\author{Aidan Sharpe}
|
||||||
|
|
||||||
|
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\begin{document}
|
||||||
|
\maketitle
|
||||||
|
|
||||||
|
\section{Introduction}
|
||||||
|
In our previous exercises, we constructed several simple CMOS gates. Specifically, we made an inverter, a transmission gate, and a two-input NAND gate. In this exercise, we combined these simple gates together to obtain more complex behaviors.
|
||||||
|
|
||||||
|
We used transmission gates and the inverter to construct a two to one multiplexer, and we used multiple NAND gates to create a half-adder.
|
||||||
|
|
||||||
|
\section{Half Adder}
|
||||||
|
A half adder is a device that has two inputs $A$ and $B$, and two outputs: the sum ($Y$) and the carry ($C$). For simplification reasons, we opted to keep our carry out inverted ($\sim C$). The relationship between the inputs and outputs is seen in table \ref{tbl:half-adder-truth}. The sum is high when the sum of $A$ and $B$ is one, and low when the sum modulo two is zero. The carry out is only high when the sum of $A$ and $B$ is two. Therefore, the inverted carry out $\sim C$ is always high unless the sum of $A$ and $B$ is two, in which case, $\sim C$ is low.
|
||||||
|
|
||||||
|
\begin{table}[h]
|
||||||
|
\center
|
||||||
|
\caption{Half Adder Truth Table}
|
||||||
|
\begin{tabular}{ c c | c c}
|
||||||
|
$A$ & $B$ & $Y$ & $\sim C$\\
|
||||||
|
\hline
|
||||||
|
0 & 0 & 0 & 1 \\
|
||||||
|
0 & 1 & 1 & 1 \\
|
||||||
|
1 & 0 & 1 & 1 \\
|
||||||
|
1 & 1 & 0 & 0 \\
|
||||||
|
\end{tabular}
|
||||||
|
\label{tbl:half-adder-truth}
|
||||||
|
\end{table}
|
||||||
|
|
||||||
|
We explored several half adder designs during this exercise, and we settled on using a simple design with four NAND gates combined as shown in figure \ref{fig:half-adder-schematic}. We ultimately decided on this design for its combination of speed and simplicity.
|
||||||
|
|
||||||
|
\begin{figure}[h]
|
||||||
|
\center\includegraphics[width=0.4\textwidth]{graphics/half-adder-schematic.png}
|
||||||
|
\caption{Symbol-level schematic for half adder}
|
||||||
|
\label{fig:half-adder-schematic}
|
||||||
|
\end{figure}
|
||||||
|
|
||||||
|
To validate our design matches the desired behavior, we assembled a simulation that tests every combination of $A$ and $B$. This was done with two square waves, each at 50\% duty cycle. The input to $A$ had a 1[ns] period of oscillation, while the input to $B$ had a 2[ns] period. Together, the signals create a two-bit binary counter. The signals from the simulation, seen in figure \ref{fig:half-adder-logic}, matched the expected behavior. The teal trace, the inverted carry out $\sim C$, is only low when both $A$ and $B$ are high. Additionally, the magenta trace, the sum $Y$, is high when only one of $A$ and $B$ is high.
|
||||||
|
|
||||||
|
|
||||||
|
\begin{figure}[h]
|
||||||
|
\center\includegraphics[width=0.4\textwidth]{graphics/half-adder-logic.png}
|
||||||
|
\caption{Logic signals for half adder}
|
||||||
|
\label{fig:half-adder-logic}
|
||||||
|
\end{figure}
|
||||||
|
|
||||||
|
Taking a closer look at the traces in figure \ref{fig:half-adder-logic}, it is important to note that rise time for the output is actually smaller than the rise time of the inputs. This effect means that the switching time for our transistors is faster than our input.
|
||||||
|
|
||||||
|
\section{Two-to-One Multiplexer}
|
||||||
|
Our two-to-one multiplexer (mux) is a signal control device. The control signal $S_0$ selects which of the two inputs $A_0$ or $A_1$ is passed to the output $Y$.
|
||||||
|
|
||||||
|
\begin{table}[h]
|
||||||
|
\center
|
||||||
|
\caption{Two-to-one multiplexer truth table}
|
||||||
|
\begin{tabular}{ c | c}
|
||||||
|
$S_0$ & $Y$ \\
|
||||||
|
\hline
|
||||||
|
0 & $A_0$ \\
|
||||||
|
1 & $A_1$ \\
|
||||||
|
\end{tabular}
|
||||||
|
\label{tbl:mux-2-1-truth}
|
||||||
|
\end{table}
|
||||||
|
|
||||||
|
Our design used two transmission gates---one for each input---to determine if the signal should be passed through or not. We also used an inverter to send the opposite control signal to one of the transmission gates. This way, only one of the two signals would be passed through at any given time. This setup is realized with a schematic in figure \ref{fig:mux-2-1-schematic}.
|
||||||
|
|
||||||
|
\begin{figure}[h]
|
||||||
|
\center\includegraphics[width=0.4\textwidth]{graphics/mux-2-1-schematic.png}
|
||||||
|
\caption{Two-to-one multiplexer schematic}
|
||||||
|
\label{fig:mux-2-1-schematic}
|
||||||
|
\end{figure}
|
||||||
|
|
||||||
|
Again, we tested that our design matched the expected behavior via simulation. We set up our control signal as a square wave with a 50\% duty cycle and a 2[ns] period of oscillation. Since transmission gates directly pass the input to the output, we are not restricted to passing a ``pure" one or zero. Therefore, to test which signal is being passed through, we set $A_0$ to 300[mV] and $A_1$ to 600[mv]. This way, as seen in figure \ref{fig:mux-2-1-logic}, when $S_0$ is low, the output is 300[mV], and when the $S_0$ is high, the output is 600[mV].
|
||||||
|
|
||||||
|
\begin{figure}[h]
|
||||||
|
\center\includegraphics[width=0.4\textwidth]{graphics/mux-2-1-logic.png}
|
||||||
|
\caption{Two-to-one multiplexer logic validation}
|
||||||
|
\label{fig:mux-2-1-logic}
|
||||||
|
\end{figure}
|
||||||
|
|
||||||
|
We confirmed our schematic matches the desired behavior, so we moved on to creating a layout. To make using multiple gates together easier, we made some modifications to our initial layouts. Most importantly, we wanted all horizontal interconnects to be on metal1 and all vertical interconnects to be on metal2. Adding this rule of thumb made routing much easier. For short runs, however, we prioritized using less vias, so metal1 runs vertically in some areas. Our final layout is seen in figure \ref{fig:mux-2-1-layout}. Another helpful modification was lining up the power rails for all designs. This modification made the rails clearly defined layout boundaries, and it also added additional space for routing interconnects.
|
||||||
|
|
||||||
|
\begin{figure}[h]
|
||||||
|
\center\includegraphics[width=0.4\textwidth]{graphics/mux-2-1-layout.png}
|
||||||
|
\caption{Layout for two-to-one multiplexer}
|
||||||
|
\label{fig:mux-2-1-layout}
|
||||||
|
\end{figure}
|
||||||
|
|
||||||
|
This process involved some unforeseen steps such as re-running DRC and LVS checks on the sub-designs, and re-spacing the elements within the sub-designs to create a more uniform top-level design.
|
||||||
|
|
||||||
|
\section{Conclusion}
|
||||||
|
This exercise proved the conclusion of the last exercise. We determined that by encapsulating fine details into lower-level designs, both higher-level schematic and layout design become much easier. For example, our half adder design used four two-input NAND gates. Each of our NAND gates contained four MOSFETs \cite{VLSICircuitsSystems}. Therefore, if we were to design the half adder at a transistor level, we would have had to lay out sixteen transistors.
|
||||||
|
|
||||||
|
Going forward, we will continue to abstract our desings away from the transistor level. For example, higher-level designs may employ the half adder symbol to effectively place all sixteen transistors and their interconnects in one click.
|
||||||
|
|
||||||
|
By building up a design layer-by-layer, a highly complex design suddenly becomes attainable.
|
||||||
|
|
||||||
|
\printbibliography
|
||||||
|
\end{document}
|