End sem 7; week 2 winter session 2025
This commit is contained in:
Aidan Sharpe
Binary file not shown.
|
After Width: | Height: | Size: 17 KiB |
BIN
7th-Semester-Fall-2024/VLSI/labs/lab-3/graphics/tran-signals.png
Normal file
BIN
7th-Semester-Fall-2024/VLSI/labs/lab-3/graphics/tran-signals.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 79 KiB |
@@ -29,9 +29,21 @@
|
||||
\newlabel{tbl:inv-delay}{{I}{3}{Inverter Delay Characteristics}{table.1}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {3}{\ignorespaces Inverter schematic symbol}}{3}{figure.3}\protected@file@percent }
|
||||
\newlabel{fig:inv-symbol}{{3}{3}{Inverter schematic symbol}{figure.3}{}}
|
||||
\@writefile{toc}{\contentsline {section}{\numberline {III}Conclusion}{3}{section.3}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {section}{\numberline {III}Transmission Gate}{3}{section.3}\protected@file@percent }
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {4}{\ignorespaces Inverter layout}}{3}{figure.4}\protected@file@percent }
|
||||
\newlabel{fig:inv-layout}{{4}{3}{Inverter layout}{figure.4}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {5}{\ignorespaces Transmission gate schematic}}{3}{figure.5}\protected@file@percent }
|
||||
\newlabel{fig:trans-schematic}{{5}{3}{Transmission gate schematic}{figure.5}{}}
|
||||
\@writefile{toc}{\contentsline {section}{\numberline {IV}NAND Gate}{3}{section.4}\protected@file@percent }
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {6}{\ignorespaces Transmission gate timing diagram}}{4}{figure.6}\protected@file@percent }
|
||||
\newlabel{fig:trans-signals}{{6}{4}{Transmission gate timing diagram}{figure.6}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {7}{\ignorespaces Transmission gate layout}}{4}{figure.7}\protected@file@percent }
|
||||
\newlabel{fig:trans-layout}{{7}{4}{Transmission gate layout}{figure.7}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {8}{\ignorespaces Two-input CMOS NAND gate schematic}}{4}{figure.8}\protected@file@percent }
|
||||
\newlabel{fig:nand-schematic}{{8}{4}{Two-input CMOS NAND gate schematic}{figure.8}{}}
|
||||
\@writefile{toc}{\contentsline {section}{\numberline {V}Conclusion}{4}{section.5}\protected@file@percent }
|
||||
\@writefile{lot}{\contentsline {table}{\numberline {II}{\ignorespaces NAND gate truth table}}{4}{table.2}\protected@file@percent }
|
||||
\newlabel{tbl:nand-truth}{{II}{4}{NAND gate truth table}{table.2}{}}
|
||||
\abx@aux@read@bbl@mdfivesum{66D8CCEED3AA0C3BA637E6C13B8A8AC2}
|
||||
\abx@aux@defaultrefcontext{0}{VLSICircuitsSystems}{nty/global//global/global}
|
||||
\gdef \@abspage@last{2}
|
||||
\gdef \@abspage@last{3}
|
||||
|
||||
49
7th-Semester-Fall-2024/VLSI/labs/lab-3/lab-3.bbl-SAVE-ERROR
Normal file
49
7th-Semester-Fall-2024/VLSI/labs/lab-3/lab-3.bbl-SAVE-ERROR
Normal file
@@ -0,0 +1,49 @@
|
||||
% $ biblatex auxiliary file $
|
||||
% $ biblatex bbl format version 3.2 $
|
||||
% Do not modify the above lines!
|
||||
%
|
||||
% This is an auxiliary file used by the 'biblatex' package.
|
||||
% This file may safely be deleted. It will be recreated by
|
||||
% biber as required.
|
||||
%
|
||||
\begingroup
|
||||
\makeatletter
|
||||
\@ifundefined{ver@biblatex.sty}
|
||||
{\@latex@error
|
||||
{Missing 'biblatex' package}
|
||||
{The bibliography requires the 'biblatex' package.}
|
||||
\aftergroup\endinput}
|
||||
{}
|
||||
\endgroup
|
||||
|
||||
|
||||
\refsection{0}
|
||||
\datalist[entry]{nty/global//global/global}
|
||||
\entry{VLSICircuitsSystems}{book}{}
|
||||
\name{author}{1}{}{%
|
||||
{{hash=7bdab0d2054f0c60f1ba24c3bdf19a4f}{%
|
||||
family={Neil\bibnamedelimb H.\bibnamedelimi E.\bibnamedelimi Weste},
|
||||
familyi={N\bibinitperiod\bibinitdelim H\bibinitperiod\bibinitdelim E\bibinitperiod\bibinitdelim W\bibinitperiod},
|
||||
given={David\bibnamedelimb Money\bibnamedelima Harris},
|
||||
giveni={D\bibinitperiod\bibinitdelim M\bibinitperiod\bibinitdelim H\bibinitperiod}}}%
|
||||
}
|
||||
\list{publisher}{1}{%
|
||||
{Pearson}%
|
||||
}
|
||||
\strng{namehash}{7bdab0d2054f0c60f1ba24c3bdf19a4f}
|
||||
\strng{fullhash}{7bdab0d2054f0c60f1ba24c3bdf19a4f}
|
||||
\strng{bibnamehash}{7bdab0d2054f0c60f1ba24c3bdf19a4f}
|
||||
\strng{authorbibnamehash}{7bdab0d2054f0c60f1ba24c3bdf19a4f}
|
||||
\strng{authornamehash}{7bdab0d2054f0c60f1ba24c3bdf19a4f}
|
||||
\strng{authorfullhash}{7bdab0d2054f0c60f1ba24c3bdf19a4f}
|
||||
\field{sortinit}{N}
|
||||
\field{sortinithash}{22369a73d5f88983a108b63f07f37084}
|
||||
\field{labelnamesource}{author}
|
||||
\field{labeltitlesource}{title}
|
||||
\field{title}{CMOS VLSI Design a Circuits and Systems Perspective, Fourth Edition}
|
||||
\field{year}{2011}
|
||||
\endentry
|
||||
\enddatalist
|
||||
\endrefsection
|
||||
\endinput
|
||||
|
||||
2251
7th-Semester-Fall-2024/VLSI/labs/lab-3/lab-3.bcf-SAVE-ERROR
Normal file
2251
7th-Semester-Fall-2024/VLSI/labs/lab-3/lab-3.bcf-SAVE-ERROR
Normal file
File diff suppressed because it is too large
Load Diff
@@ -1,15 +1,15 @@
|
||||
[0] Config.pm:307> INFO - This is Biber 2.19
|
||||
[0] Config.pm:310> INFO - Logfile is 'lab-3.blg'
|
||||
[108] biber:340> INFO - === Tue Nov 19, 2024, 19:56:21
|
||||
[127] Biber.pm:419> INFO - Reading 'lab-3.bcf'
|
||||
[215] Biber.pm:979> INFO - Found 1 citekeys in bib section 0
|
||||
[232] Biber.pm:4419> INFO - Processing section 0
|
||||
[247] Biber.pm:4610> INFO - Looking for bibtex file 'references.bib' for section 0
|
||||
[248] bibtex.pm:1713> INFO - LaTeX decoding ...
|
||||
[252] bibtex.pm:1519> INFO - Found BibTeX data source 'references.bib'
|
||||
[298] UCollate.pm:68> INFO - Overriding locale 'en-US' defaults 'normalization = NFD' with 'normalization = prenormalized'
|
||||
[298] UCollate.pm:68> INFO - Overriding locale 'en-US' defaults 'variable = shifted' with 'variable = non-ignorable'
|
||||
[298] Biber.pm:4239> INFO - Sorting list 'nty/global//global/global' of type 'entry' with template 'nty' and locale 'en-US'
|
||||
[298] Biber.pm:4245> INFO - No sort tailoring available for locale 'en-US'
|
||||
[300] bbl.pm:660> INFO - Writing 'lab-3.bbl' with encoding 'UTF-8'
|
||||
[300] bbl.pm:763> INFO - Output to lab-3.bbl
|
||||
[73] biber:340> INFO - === Sun Dec 8, 2024, 20:13:44
|
||||
[85] Biber.pm:419> INFO - Reading 'lab-3.bcf'
|
||||
[146] Biber.pm:979> INFO - Found 1 citekeys in bib section 0
|
||||
[157] Biber.pm:4419> INFO - Processing section 0
|
||||
[166] Biber.pm:4610> INFO - Looking for bibtex file 'references.bib' for section 0
|
||||
[167] bibtex.pm:1713> INFO - LaTeX decoding ...
|
||||
[169] bibtex.pm:1519> INFO - Found BibTeX data source 'references.bib'
|
||||
[200] UCollate.pm:68> INFO - Overriding locale 'en-US' defaults 'variable = shifted' with 'variable = non-ignorable'
|
||||
[200] UCollate.pm:68> INFO - Overriding locale 'en-US' defaults 'normalization = NFD' with 'normalization = prenormalized'
|
||||
[200] Biber.pm:4239> INFO - Sorting list 'nty/global//global/global' of type 'entry' with template 'nty' and locale 'en-US'
|
||||
[200] Biber.pm:4245> INFO - No sort tailoring available for locale 'en-US'
|
||||
[201] bbl.pm:660> INFO - Writing 'lab-3.bbl' with encoding 'UTF-8'
|
||||
[202] bbl.pm:763> INFO - Output to lab-3.bbl
|
||||
|
||||
@@ -1,13 +1,14 @@
|
||||
# Fdb version 4
|
||||
["biber lab-3"] 1732064180.21414 "lab-3.bcf" "lab-3.bbl" "lab-3" 1732074596.72708 0
|
||||
"lab-3.bcf" 1732074596.55002 107849 19388b857c8fbe58213de7619cc8a2ee "pdflatex"
|
||||
["biber lab-3"] 1733706824.00038 "lab-3.bcf" "lab-3.bbl" "lab-3" 1733837717.2406 0
|
||||
"lab-3.bcf" 1733837716.97826 107849 19388b857c8fbe58213de7619cc8a2ee "pdflatex"
|
||||
"references.bib" 1732049306.41364 558 df972a2d65f28e8a8ecebb4ee0b82d70 ""
|
||||
(generated)
|
||||
"lab-3.bbl"
|
||||
"lab-3.blg"
|
||||
(rewritten before read)
|
||||
["pdflatex"] 1732074594.91744 "lab-3.tex" "lab-3.pdf" "lab-3" 1732074596.72758 0
|
||||
["pdflatex"] 1733837714.16973 "lab-3.tex" "lab-3.pdf" "lab-3" 1733837717.24107 0
|
||||
"/usr/share/texlive/texmf-dist/fonts/enc/dvips/lm/lm-mathit.enc" 1202520719 2405 5dcf2c1b967ee25cc46c58cd52244aed ""
|
||||
"/usr/share/texlive/texmf-dist/fonts/enc/dvips/lm/lm-mathsy.enc" 1202520719 2840 216e6e45ad352e2456e1149f28885bee ""
|
||||
"/usr/share/texlive/texmf-dist/fonts/enc/dvips/lm/lm-rm.enc" 1202520719 2327 9d6df24f9c4f7368395224341a95523a ""
|
||||
"/usr/share/texlive/texmf-dist/fonts/enc/dvips/lm/lm-rmsc.enc" 1202520719 2355 3e74b90173fc699673a5163cee277702 ""
|
||||
"/usr/share/texlive/texmf-dist/fonts/map/fontname/texfonts.map" 1577235249 3524 cb3e574dea2d1052e39280babc910dc8 ""
|
||||
@@ -62,6 +63,7 @@
|
||||
"/usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr7.pfb" 1255129361 121145 68312a933e2c689ed40ec0aba373e279 ""
|
||||
"/usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr8.pfb" 1255129361 122174 a7a08406857c9530a0320a2517f60370 ""
|
||||
"/usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmri10.pfb" 1255129361 112593 fda2373ba4420af33949610de4c28fe8 ""
|
||||
"/usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmsy10.pfb" 1254269338 27863 09ce3735688ffde955e72da27c95b61a ""
|
||||
"/usr/share/texlive/texmf-dist/tex/context/base/mkii/supp-pdf.mkii" 1714953600 71627 94eb9990bed73c364d7f53f960cc8c5b ""
|
||||
"/usr/share/texlive/texmf-dist/tex/generic/atbegshi/atbegshi.sty" 1575674566 24708 5584a51a7101caf7e6bbf1fc27d8f7b1 ""
|
||||
"/usr/share/texlive/texmf-dist/tex/generic/bigintcalc/bigintcalc.sty" 1576625341 40635 c40361e206be584d448876bba8a64a3b ""
|
||||
@@ -295,11 +297,15 @@
|
||||
"graphics/inv-schematic.png" 1732050701 9712 44f058748b77baca7828a2e84ecc8acb ""
|
||||
"graphics/inv-symbol.png" 1732071169 5870 e9b1b0f9ba66f5d331c6491cf3769cc4 ""
|
||||
"graphics/inverter-pins-io.png" 1730826169.35618 82578 2f12d40c77d52c168a5c697b06baefa4 ""
|
||||
"lab-3.aux" 1732074596.54602 2366 0c1791cc00ff9647d4451a288f4d8eee "pdflatex"
|
||||
"lab-3.bbl" 1732064181.38164 1765 66d8cceed3aa0c3ba637e6c13b8a8ac2 "biber lab-3"
|
||||
"lab-3.out" 1732074596.54702 279 27d4c9a85c014344d4809060353b15ed "pdflatex"
|
||||
"lab-3.run.xml" 1732074596.55102 2312 3ea7060cdcc1885fd98bc9f105caf70a "pdflatex"
|
||||
"lab-3.tex" 1732074593.332 8696 7f669cd7950e190e50ccf1713d2bf7da ""
|
||||
"graphics/nand-schematic.png" 1733694810 17637 c82e8dde09f1a7fe46a7c518207a367b ""
|
||||
"graphics/tran-layout.png" 1732033487 29244 37e2234bec907ea28b2094e016571213 ""
|
||||
"graphics/tran-schematic.png" 1732033469 10769 4ce6e6c9b8bfa9f3d48f17d0689ba744 ""
|
||||
"graphics/tran-signals.png" 1733690122 80792 f54ab8e41446e7dbe2d57ab9f5845c53 ""
|
||||
"lab-3.aux" 1733837716.97226 3671 e45a326edc3fd9e2a61ff5124dded788 "pdflatex"
|
||||
"lab-3.bbl" 1733706824.70057 1765 66d8cceed3aa0c3ba637e6c13b8a8ac2 "biber lab-3"
|
||||
"lab-3.out" 1733837716.97326 501 3401e8f663ae5378a848fadc150f11ae "pdflatex"
|
||||
"lab-3.run.xml" 1733837716.97926 2312 3ea7060cdcc1885fd98bc9f105caf70a "pdflatex"
|
||||
"lab-3.tex" 1733837713.57425 11698 2033e2bea4730c501e39ebe70d420dc1 ""
|
||||
(generated)
|
||||
"lab-3.aux"
|
||||
"lab-3.bcf"
|
||||
|
||||
@@ -1378,10 +1378,31 @@ INPUT ./graphics/inv-layout.png
|
||||
INPUT graphics/inv-layout.png
|
||||
INPUT ./graphics/inv-layout.png
|
||||
INPUT ./graphics/inv-layout.png
|
||||
INPUT ./graphics/tran-schematic.png
|
||||
INPUT ./graphics/tran-schematic.png
|
||||
INPUT graphics/tran-schematic.png
|
||||
INPUT ./graphics/tran-schematic.png
|
||||
INPUT ./graphics/tran-schematic.png
|
||||
INPUT ./graphics/tran-signals.png
|
||||
INPUT ./graphics/tran-signals.png
|
||||
INPUT graphics/tran-signals.png
|
||||
INPUT ./graphics/tran-signals.png
|
||||
INPUT ./graphics/tran-signals.png
|
||||
INPUT ./graphics/tran-layout.png
|
||||
INPUT ./graphics/tran-layout.png
|
||||
INPUT graphics/tran-layout.png
|
||||
INPUT ./graphics/tran-layout.png
|
||||
INPUT ./graphics/tran-layout.png
|
||||
INPUT /var/lib/texmf/fonts/map/pdftex/updmap/pdftex.map
|
||||
INPUT /usr/share/texlive/texmf-dist/fonts/enc/dvips/lm/lm-rm.enc
|
||||
INPUT /usr/share/texlive/texmf-dist/fonts/enc/dvips/lm/lm-rmsc.enc
|
||||
INPUT /usr/share/texlive/texmf-dist/fonts/enc/dvips/lm/lm-mathit.enc
|
||||
INPUT ./graphics/nand-schematic.png
|
||||
INPUT ./graphics/nand-schematic.png
|
||||
INPUT graphics/nand-schematic.png
|
||||
INPUT ./graphics/nand-schematic.png
|
||||
INPUT ./graphics/nand-schematic.png
|
||||
INPUT /usr/share/texlive/texmf-dist/fonts/enc/dvips/lm/lm-mathsy.enc
|
||||
INPUT lab-3.aux
|
||||
INPUT ./lab-3.out
|
||||
INPUT ./lab-3.out
|
||||
@@ -1399,3 +1420,4 @@ INPUT /usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr6.pfb
|
||||
INPUT /usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr7.pfb
|
||||
INPUT /usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr8.pfb
|
||||
INPUT /usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmri10.pfb
|
||||
INPUT /usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmsy10.pfb
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
This is pdfTeX, Version 3.141592653-2.6-1.40.25 (TeX Live 2023/Fedora 40) (preloaded format=pdflatex 2024.11.12) 19 NOV 2024 22:49
|
||||
This is pdfTeX, Version 3.141592653-2.6-1.40.25 (TeX Live 2023/Fedora 40) (preloaded format=pdflatex 2024.11.12) 10 DEC 2024 08:35
|
||||
entering extended mode
|
||||
restricted \write18 enabled.
|
||||
file:line:error style messages enabled.
|
||||
@@ -1201,12 +1201,12 @@ LaTeX Font Info: Font shape `OT1/ptm/bx/n' in size <7.4> not available
|
||||
(Font) Font shape `OT1/ptm/b/n' tried instead on input line 68.
|
||||
LaTeX Font Info: Font shape `OT1/ptm/bx/n' in size <6> not available
|
||||
(Font) Font shape `OT1/ptm/b/n' tried instead on input line 68.
|
||||
<graphics/inv-schematic.png, id=21, 569.12625pt x 666.23906pt>
|
||||
<graphics/inv-schematic.png, id=29, 569.12625pt x 666.23906pt>
|
||||
File: graphics/inv-schematic.png Graphic file (type png)
|
||||
<use graphics/inv-schematic.png>
|
||||
Package pdftex.def Info: graphics/inv-schematic.png used on input line 71.
|
||||
(pdftex.def) Requested size: 222.58856pt x 260.5743pt.
|
||||
<graphics/inverter-pins-io.png, id=24, 1422.81563pt x 642.90187pt>
|
||||
<graphics/inverter-pins-io.png, id=32, 1422.81563pt x 642.90187pt>
|
||||
File: graphics/inverter-pins-io.png Graphic file (type png)
|
||||
<use graphics/inverter-pins-io.png>
|
||||
Package pdftex.def Info: graphics/inverter-pins-io.png used on input line 85.
|
||||
@@ -1218,12 +1218,12 @@ LaTeX Font Info: External font `lmex10' loaded for size
|
||||
|
||||
Underfull \vbox (badness 10000) has occurred while \output is active []
|
||||
|
||||
<graphics/inv-symbol.png, id=28, 584.1825pt x 304.88907pt>
|
||||
<graphics/inv-symbol.png, id=36, 584.1825pt x 304.88907pt>
|
||||
File: graphics/inv-symbol.png Graphic file (type png)
|
||||
<use graphics/inv-symbol.png>
|
||||
Package pdftex.def Info: graphics/inv-symbol.png used on input line 112.
|
||||
(pdftex.def) Requested size: 222.58856pt x 116.17075pt.
|
||||
<graphics/inv-layout.png, id=30, 575.14874pt x 599.23875pt>
|
||||
<graphics/inv-layout.png, id=38, 575.14874pt x 599.23875pt>
|
||||
File: graphics/inv-layout.png Graphic file (type png)
|
||||
<use graphics/inv-layout.png>
|
||||
Package pdftex.def Info: graphics/inv-layout.png used on input line 120.
|
||||
@@ -1232,6 +1232,43 @@ Package pdftex.def Info: graphics/inv-layout.png used on input line 120.
|
||||
|
||||
LaTeX Warning: `h' float specifier changed to `ht'.
|
||||
|
||||
<graphics/tran-schematic.png, id=40, 569.12625pt x 666.23906pt>
|
||||
File: graphics/tran-schematic.png Graphic file (type png)
|
||||
<use graphics/tran-schematic.png>
|
||||
Package pdftex.def Info: graphics/tran-schematic.png used on input line 130.
|
||||
(pdftex.def) Requested size: 222.58856pt x 260.5743pt.
|
||||
|
||||
LaTeX Warning: `h' float specifier changed to `ht'.
|
||||
|
||||
<graphics/tran-signals.png, id=41, 1422.81563pt x 642.90187pt>
|
||||
File: graphics/tran-signals.png Graphic file (type png)
|
||||
<use graphics/tran-signals.png>
|
||||
Package pdftex.def Info: graphics/tran-signals.png used on input line 138.
|
||||
(pdftex.def) Requested size: 222.58856pt x 100.57088pt.
|
||||
|
||||
LaTeX Warning: `h' float specifier changed to `ht'.
|
||||
|
||||
<graphics/tran-layout.png, id=43, 575.14874pt x 599.23875pt>
|
||||
File: graphics/tran-layout.png Graphic file (type png)
|
||||
<use graphics/tran-layout.png>
|
||||
Package pdftex.def Info: graphics/tran-layout.png used on input line 146.
|
||||
(pdftex.def) Requested size: 222.58856pt x 231.91002pt.
|
||||
|
||||
LaTeX Warning: `h' float specifier changed to `ht'.
|
||||
|
||||
|
||||
LaTeX Warning: `h' float specifier changed to `ht'.
|
||||
|
||||
[2{/var/lib/texmf/fonts/map/pdftex/updmap/pdftex.map}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/lm/lm-rm.enc}
|
||||
|
||||
|
||||
{/usr/share/texlive/texmf-dist/fonts/enc/dvips/lm/lm-rmsc.enc}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/lm/lm-mathit.enc} <./graphics/inv-schematic.png> <./graphics/inverter-pins-io.png>]
|
||||
<graphics/nand-schematic.png, id=66, 1288.815pt x 665.48625pt>
|
||||
File: graphics/nand-schematic.png Graphic file (type png)
|
||||
<use graphics/nand-schematic.png>
|
||||
Package pdftex.def Info: graphics/nand-schematic.png used on input line 174.
|
||||
(pdftex.def) Requested size: 222.58856pt x 114.9285pt.
|
||||
|
||||
|
||||
** Conference Paper **
|
||||
Before submitting the final camera ready copy, remember to:
|
||||
@@ -1243,29 +1280,26 @@ Before submitting the final camera ready copy, remember to:
|
||||
uses only Type 1 fonts and that every step in the generation
|
||||
process uses the appropriate paper size.
|
||||
|
||||
[2{/var/lib/texmf/fonts/map/pdftex/updmap/pdftex.map}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/lm/lm-rm.enc}
|
||||
|
||||
|
||||
{/usr/share/texlive/texmf-dist/fonts/enc/dvips/lm/lm-rmsc.enc}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/lm/lm-mathit.enc} <./graphics/inv-schematic.png> <./graphics/inverter-pins-io.png>] [3 <./graphics/inv-symbol.png> <./graphics/inv-layout.png>] (./lab-3.aux)
|
||||
[3{/usr/share/texlive/texmf-dist/fonts/enc/dvips/lm/lm-mathsy.enc} <./graphics/inv-symbol.png> <./graphics/inv-layout.png> <./graphics/tran-schematic.png>] [4 <./graphics/tran-signals.png> <./graphics/tran-layout.png> <./graphics/nand-schematic.png>] (./lab-3.aux)
|
||||
Package rerunfilecheck Info: File `lab-3.out' has not changed.
|
||||
(rerunfilecheck) Checksum: 27D4C9A85C014344D4809060353B15ED;279.
|
||||
(rerunfilecheck) Checksum: 3401E8F663AE5378A848FADC150F11AE;501.
|
||||
Package logreq Info: Writing requests to 'lab-3.run.xml'.
|
||||
\openout1 = `lab-3.run.xml'.
|
||||
|
||||
)
|
||||
Here is how much of TeX's memory you used:
|
||||
60640 strings out of 476041
|
||||
1526381 string characters out of 5793163
|
||||
2609236 words of memory out of 6000000
|
||||
80367 multiletter control sequences out of 15000+600000
|
||||
60684 strings out of 476041
|
||||
1527382 string characters out of 5793163
|
||||
2609484 words of memory out of 6000000
|
||||
80398 multiletter control sequences out of 15000+600000
|
||||
696086 words of font info for 142 fonts, out of 8000000 for 9000
|
||||
1140 hyphenation exceptions out of 8191
|
||||
117i,12n,118p,1155b,1479s stack positions out of 10000i,1000n,20000p,200000b,200000s
|
||||
</usr/share/texlive/texmf-dist/fonts/type1/public/amsfonts/cm/cmr12.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmcsc10.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmmi10.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmmi6.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmmi7.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmmi8.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr10.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr12.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr6.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr7.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr8.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmri10.pfb>
|
||||
Output written on lab-3.pdf (2 pages, 327989 bytes).
|
||||
117i,12n,118p,1147b,1479s stack positions out of 10000i,1000n,20000p,200000b,200000s
|
||||
</usr/share/texlive/texmf-dist/fonts/type1/public/amsfonts/cm/cmr12.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmcsc10.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmmi10.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmmi6.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmmi7.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmmi8.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr10.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr12.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr6.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr7.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr8.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmri10.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmsy10.pfb>
|
||||
Output written on lab-3.pdf (3 pages, 472371 bytes).
|
||||
PDF statistics:
|
||||
123 PDF objects out of 1000 (max. 8388607)
|
||||
86 compressed objects within 1 object stream
|
||||
14 named destinations out of 1000 (max. 500000)
|
||||
57 words of extra memory for PDF output out of 10000 (max. 10000000)
|
||||
160 PDF objects out of 1000 (max. 8388607)
|
||||
111 compressed objects within 2 object streams
|
||||
22 named destinations out of 1000 (max. 500000)
|
||||
93 words of extra memory for PDF output out of 10000 (max. 10000000)
|
||||
|
||||
|
||||
@@ -1,3 +1,5 @@
|
||||
\BOOKMARK [1][-]{section.1}{\376\377\000I\000n\000t\000r\000o\000d\000u\000c\000t\000i\000o\000n}{}% 1
|
||||
\BOOKMARK [1][-]{section.2}{\376\377\000I\000n\000v\000e\000r\000t\000e\000r}{}% 2
|
||||
\BOOKMARK [1][-]{section.3}{\376\377\000C\000o\000n\000c\000l\000u\000s\000i\000o\000n}{}% 3
|
||||
\BOOKMARK [1][-]{section.3}{\376\377\000T\000r\000a\000n\000s\000m\000i\000s\000s\000i\000o\000n\000\040\000G\000a\000t\000e}{}% 3
|
||||
\BOOKMARK [1][-]{section.4}{\376\377\000N\000A\000N\000D\000\040\000G\000a\000t\000e}{}% 4
|
||||
\BOOKMARK [1][-]{section.5}{\376\377\000C\000o\000n\000c\000l\000u\000s\000i\000o\000n}{}% 5
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -65,7 +65,7 @@ In this lab, we designed and analyzed several simple CMOS gates. Specifically, w
|
||||
\section{Inverter}
|
||||
The first, and simplest gate we created was a CMOS inverter. This device is made from one n-channel MOSFET (NMOS), and one p-channel MOSFET (PMOS). Its schematic is seen in figure \ref{fig:inv-sch}. Looking closely, the width of the NMOS is 120nm and the width of the PMOS is 240nm. This was done to match the resistances of the two devices.
|
||||
|
||||
The equivalent channel resistance of an NMOS is $R = \frac{R_0}{k}$, and for a PMOS, $R = \frac{2R_0}{k}$ \cite{VLSICircuitsSystems}. The constant $k$ is the ratio of the width of the MOSFET to the width of a unit transistor for that technology. For example, the unit transistor for 45nm is 120nm. Therefore, a PMOS will always have twice the resistance of an NMOS for the same width, and if the resistances are to match, then the PMOS must be twice as wide as the NMOS.
|
||||
The equivalent channel resistance of an NMOS is $R_n = \frac{R}{k}$, and for a PMOS, $R_p = \frac{2R}{k}$ \cite{VLSICircuitsSystems}. The constant $k$ is the ratio of the width of the MOSFET to the width of a unit transistor for that technology. For example, the unit transistor for our 45[nm] design library is 120[nm]. Therefore, a PMOS will always have twice the resistance of an NMOS of the same width, and if the resistances are to match, then the PMOS must be twice as wide as the NMOS.
|
||||
|
||||
\begin{figure}[h]
|
||||
\center\includegraphics[width=0.4\textwidth]{graphics/inv-schematic.png}
|
||||
@@ -87,7 +87,7 @@ For our inverter, we simulated a pulsed input with a period of 2[ns], seen as th
|
||||
\label{fig:inverter-io}
|
||||
\end{figure}
|
||||
|
||||
Instead of eyeballing the time, we loaded the outputs of the simulation into a calculator tool to precisely calculate the time. This tool was used to calculate all five delay characteristics. The values of the delay characteristics are seen in table \ref{tbl:inv-delay}. It is important to note that the rise and fall times of the input signal are identical, but as seen in the table, the rise and fall times for the output are different. This effect is quite odd. The total output capacitance is $3C_0$ regardless of whether the output is rising or falling, and we picked our $k$ values such that the resistance was $R_0$ for both the pull-up and pull-down network. Therefore, regardless of the edge, the time constant should be $\tau = 3R_0C_0$. Regardless, we still have a difference between the rising and falling edges. The difference likely comes from an assumption we made. We assumed that the resistance for a PMOS is twice that of an NMOS of the same size, but this is merely an approximation to account for holes having lower mobility than electrons\cite{VLSICircuitsSystems}.
|
||||
Instead of eyeballing the time, we loaded the outputs of the simulation into a calculator tool to precisely calculate the time. This tool was used to calculate all five delay characteristics. The values of the delay characteristics are seen in table \ref{tbl:inv-delay}. It is important to note that the rise and fall times of the input signal are identical, but as seen in the table, the rise and fall times for the output are different. This effect is quite odd. The total output capacitance is $3C$ regardless of whether the output is rising or falling, and we picked our $k$ values such that the resistance was $R$ for both the pull-up and pull-down network. Therefore, regardless of the edge, the time constant should be $\tau = 3RC$. Regardless, we still have a difference between the rising and falling edges. The difference likely comes from an assumption we made. We assumed that the resistance for a PMOS is twice that of an NMOS of the same size, but this is merely an approximation to account for holes having lower mobility than electrons\cite{VLSICircuitsSystems}.
|
||||
|
||||
\begin{table}[H]
|
||||
\center
|
||||
@@ -124,10 +124,62 @@ Finally, we created the phyical layout for the inverter. The layout for the MOSF
|
||||
|
||||
To ensure that our layout met the design rules imposed by the technology library, we used a design rule checker. Our initial design had some small errors, such as the n-well being too close to the contacts to power, but the design rule checker enabled us to rapidly resolve these issues. We also ran another check to ensure that the connections in the layout matched the connections in the schematic. After adding the proper pins, this check also passed. With both checks completed, our inverter was finished.
|
||||
|
||||
\section{Conclusion}
|
||||
The workflow implemented enables the rapid re-use of circuits. This concept is important as it is not feasible to layout every MOSFET and every connection in a larger design. By building up a design from previously designed components, keeping track of the characteristics of each piece along the way, it is much easier to create complex digital circuits.
|
||||
\section{Transmission Gate}
|
||||
A transmission gate is similar in construction to an inverter, consisting of one NMOS and one PMOS. A schematic for a CMOS transmission gate is seen in figure \ref{fig:trans-schematic}. When $C$ is low ($\sim C$ is high), the output $Y$ is the same as the input $A$, and when $C$ is high ($\sim C$ is low), the output $Y$ is floating. The transmission gate works well in this layout because the PMOS passes a "strong one" and the NMOS passes a "strong zero".
|
||||
\begin{figure}[h]
|
||||
\center\includegraphics[width=0.4\textwidth]{graphics/tran-schematic.png}
|
||||
\caption{Transmission gate schematic}
|
||||
\label{fig:trans-schematic}
|
||||
\end{figure}
|
||||
|
||||
This process is the essence of VLSI. It is not possible for people to build a CPU with billions of transistors one MOSFET at a time. Very large scale designs are only made possible by slowly building up a subsystem by using repeatable elements, and abstracting away the fine details.
|
||||
With only one transmission gate, the output signal quality is very good. One thing to keep in mind, however, is that unlike an inverter, where the output power comes from the rails, with a transmission gate, the output power comes directly from the input. Therefore, any noise present in the input will get passed to the output. With a standard CMOS gate, the output noise does not build from stage to stage.
|
||||
|
||||
\begin{figure}[h]
|
||||
\center\includegraphics[width=0.4\textwidth]{graphics/tran-signals.png}
|
||||
\caption{Transmission gate timing diagram}
|
||||
\label{fig:trans-signals}
|
||||
\end{figure}
|
||||
|
||||
When it comes to the pysical layout of the transmission gate shown in figure \ref{fig:trans-layout}, one thing to keep in mind is that $C$ and $\sim C$ are inaccessible on metal1. Therefore, an additional via---metal1 to metal2---would be required for each of the two control inputs.
|
||||
|
||||
\begin{figure}[h]
|
||||
\center\includegraphics[width=0.4\textwidth]{graphics/tran-layout.png}
|
||||
\caption{Transmission gate layout}
|
||||
\label{fig:trans-layout}
|
||||
\end{figure}
|
||||
|
||||
|
||||
\section{NAND Gate}
|
||||
The NAND gate is the fastest two input CMOS logic gate. It has an input capacitance of 4C compared to the 5C of a NOR gate. The truth table for a NAND is seen in table \ref{tbl:nand-truth}. The output is low only when all inputs are high.
|
||||
|
||||
\begin{table}[h]
|
||||
\center
|
||||
\caption{NAND gate truth table}
|
||||
\begin{tabular}{c c | c}
|
||||
A & B & X\\
|
||||
\hline
|
||||
0 & 0 & 1\\
|
||||
0 & 1 & 1\\
|
||||
1 & 0 & 1\\
|
||||
1 & 1 & 0\\
|
||||
\end{tabular}
|
||||
\label{tbl:nand-truth}
|
||||
\end{table}
|
||||
|
||||
The simplest two-input CMOS NAND gate has a pull-up network with two PMOS's in series and a pull-down network with two NMOS's in parallel, seen in figure \ref{fig:nand-schematic}. To establish the same resistance in both networks, all gates are twice the size of a unit transistor. Since the input capacitance is the sum of all gate capacitances for a given input, and the gate capacitance for both n-channel and p-channel MOSFETs is $kC$, we have a total input capacitance of $2C + 2C = 4C$.
|
||||
|
||||
For our 45[nm] technology package, the unit transistor is 120[nm]. Therfore all transistors will have a width of 240[nm]
|
||||
|
||||
\begin{figure}[h]
|
||||
\center\includegraphics[width=0.4\textwidth]{graphics/nand-schematic.png}
|
||||
\caption{Two-input CMOS NAND gate schematic}
|
||||
\label{fig:nand-schematic}
|
||||
\end{figure}
|
||||
|
||||
\section{Conclusion}
|
||||
The workflow implemented enables the rapid re-use of circuits. This concept is important as it is not feasible to lay out every MOSFET and every connection in a larger design. By building up a design from previously designed components, keeping track of the characteristics of each piece along the way, it is much easier to create complex digital circuits.
|
||||
|
||||
This process is the essence of VLSI. It is not possible for people to build a CPU with millions or billions of transistors one MOSFET at a time. Very large scale designs are only made possible by slowly building up a subsystem by using repeatable elements, and abstracting away the fine details.
|
||||
|
||||
\printbibliography
|
||||
\end{document}
|
||||
|
||||
Reference in New Issue
Block a user