diff --git a/6th-Semester-Spring-2024/DSP/Labs/Lab-04/lab4-1.py b/6th-Semester-Spring-2024/DSP/Labs/Lab-04/lab4-1.py
index 387ebad..4b88593 100644
--- a/6th-Semester-Spring-2024/DSP/Labs/Lab-04/lab4-1.py
+++ b/6th-Semester-Spring-2024/DSP/Labs/Lab-04/lab4-1.py
@@ -2,6 +2,16 @@ import numpy as np
import matplotlib.pyplot as plt
N = 8
+
+# Analytic DFT
+k = np.arange(N)
+W_N = np.exp(-2j*np.pi*k/N)
+plt.stem(k, -W_N)
+plt.xlabel("$k$")
+plt.ylabel("$W_N$")
+plt.show()
+
+
n = np.arange(N)
x = (-1.0)**n
DFT_8_point = np.fft.fft(x, 8)
diff --git a/6th-Semester-Spring-2024/EnI/Group Work/code/ReadAcceleration/ReadAcceleration.ino b/6th-Semester-Spring-2024/EnI/Group Work/code/ReadAcceleration/ReadAcceleration.ino
index 918470d..741aabf 100644
--- a/6th-Semester-Spring-2024/EnI/Group Work/code/ReadAcceleration/ReadAcceleration.ino
+++ b/6th-Semester-Spring-2024/EnI/Group Work/code/ReadAcceleration/ReadAcceleration.ino
@@ -4,7 +4,7 @@
#define SAMPLES_PER_MINUTE 256
#define SENSITIVITY 5
-#define THRESHOLD 0.04
+#define THRESHOLD 0.2
#define ID 1
#define DEBUG false
diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/.~lock.Systems_and_Control_Project_Final_Project_Spring_2024_1_11.docx# b/6th-Semester-Spring-2024/SysCon/Final Project/.~lock.Systems_and_Control_Project_Final_Project_Spring_2024_1_11.docx#
new file mode 100644
index 0000000..bdb599f
--- /dev/null
+++ b/6th-Semester-Spring-2024/SysCon/Final Project/.~lock.Systems_and_Control_Project_Final_Project_Spring_2024_1_11.docx#
@@ -0,0 +1 @@
+,sharpe,dhcp-150-250-221-141,16.04.2024 10:35,file:///home/sharpe/.var/app/org.libreoffice.LibreOffice/config/libreoffice/4;
\ No newline at end of file
diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/BuckBoost.asc b/6th-Semester-Spring-2024/SysCon/Final Project/BuckBoost.asc
new file mode 100644
index 0000000..f2a6c7c
--- /dev/null
+++ b/6th-Semester-Spring-2024/SysCon/Final Project/BuckBoost.asc
@@ -0,0 +1,49 @@
+Version 4
+SHEET 1 880 680
+WIRE 0 64 -64 64
+WIRE 176 64 96 64
+WIRE 224 64 176 64
+WIRE 320 64 288 64
+WIRE 416 64 320 64
+WIRE 176 80 176 64
+WIRE 320 80 320 64
+WIRE 416 80 416 64
+WIRE -64 96 -64 64
+WIRE 80 128 80 112
+WIRE -64 240 -64 176
+WIRE 80 240 80 208
+WIRE 80 240 -64 240
+WIRE 176 240 176 160
+WIRE 176 240 80 240
+WIRE 320 240 320 144
+WIRE 320 240 176 240
+WIRE 416 240 416 160
+WIRE 416 240 320 240
+WIRE -64 272 -64 240
+FLAG -64 272 0
+SYMBOL voltage -64 80 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V1
+SYMATTR Value 12
+SYMBOL res 400 64 R0
+SYMATTR InstName R1
+SYMATTR Value 100
+SYMBOL cap 304 80 R0
+SYMATTR InstName C1
+SYMATTR Value 1m
+SYMBOL ind 160 64 R0
+SYMATTR InstName L1
+SYMATTR Value 450m
+SYMBOL diode 288 48 R90
+WINDOW 0 0 32 VBottom 2
+WINDOW 3 32 32 VTop 2
+SYMATTR InstName D1
+SYMBOL nmos 0 112 R270
+SYMATTR InstName M1
+SYMBOL voltage 80 112 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V2
+SYMATTR Value PULSE(0 5 0 1n 1n 0.0004 0.001)
+TEXT -98 296 Left 2 !.tran 2
diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/BuckBoost.log b/6th-Semester-Spring-2024/SysCon/Final Project/BuckBoost.log
new file mode 100644
index 0000000..f7cdeba
--- /dev/null
+++ b/6th-Semester-Spring-2024/SysCon/Final Project/BuckBoost.log
@@ -0,0 +1,22 @@
+Circuit: * C:\users\sharpe\Documents\Rowan\Rowan-Classes\6th-Semester-Spring-2024\SysCon\Final Project\BuckBoost.asc
+
+Direct Newton iteration for .op point succeeded.
+
+Date: Tue Apr 16 10:31:36 2024
+Total elapsed time: 1.018 seconds.
+
+tnom = 27
+temp = 27
+method = modified trap
+totiter = 408437
+traniter = 408431
+tranpoints = 143631
+accept = 133580
+rejected = 10051
+matrix size = 10
+fillins = 0
+solver = Normal
+Avg thread counts: 1.0/1.0/1.0/1.0
+Matrix Compiler1: 480 bytes object code size 0.2/0.2/[0.1]
+Matrix Compiler2: 734 bytes object code size 0.1/0.2/[0.1]
+
diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/BuckBoost.net b/6th-Semester-Spring-2024/SysCon/Final Project/BuckBoost.net
new file mode 100644
index 0000000..00736f8
--- /dev/null
+++ b/6th-Semester-Spring-2024/SysCon/Final Project/BuckBoost.net
@@ -0,0 +1,16 @@
+* C:\users\sharpe\Documents\Rowan\Rowan-Classes\6th-Semester-Spring-2024\SysCon\Final Project\BuckBoost.asc
+V1 N001 0 12
+R1 N003 0 100
+C1 N003 0 1m
+L1 N002 0 450m
+D1 N003 N002 D
+M1 N001 N004 N002 N002 Si7336ADP
+V2 N004 0 PULSE(0 5 0 1n 1n 0.0004 0.001)
+.model D D
+.lib C:\users\sharpe\AppData\Local\LTspice\lib\cmp\standard.dio
+.model NMOS NMOS
+.model PMOS PMOS
+.lib C:\users\sharpe\AppData\Local\LTspice\lib\cmp\standard.mos
+.tran 1.5
+.backanno
+.end
diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/BuckBoost.op.raw b/6th-Semester-Spring-2024/SysCon/Final Project/BuckBoost.op.raw
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index 0000000..3ee7b46
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index 0000000..16fa01e
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diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/Topic_closed_loop_Module_2students.slx b/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/Topic_closed_loop_Module_2students.slx
new file mode 100644
index 0000000..fcd2444
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diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/Topic_open_loop_2students.slx b/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/Topic_open_loop_2students.slx
new file mode 100644
index 0000000..742f0bc
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diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/Topic_open_loop_2students.slxc b/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/Topic_open_loop_2students.slxc
new file mode 100644
index 0000000..a012414
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diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/accel/Topic_open_loop_2students/Topic_open_loop_2students_top_vm.bc b/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/accel/Topic_open_loop_2students/Topic_open_loop_2students_top_vm.bc
new file mode 100644
index 0000000..97e74a1
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diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/accel/Topic_open_loop_2students/amsi_serial.mat b/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/accel/Topic_open_loop_2students/amsi_serial.mat
new file mode 100644
index 0000000..aefa766
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diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/accel/Topic_open_loop_2students/tmwinternal/simulink_cache.xml b/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/accel/Topic_open_loop_2students/tmwinternal/simulink_cache.xml
new file mode 100644
index 0000000..6671681
--- /dev/null
+++ b/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/accel/Topic_open_loop_2students/tmwinternal/simulink_cache.xml
@@ -0,0 +1,6 @@
+
+
+
+ FsNdBVIwoIz8t9SYuH3U8w==
+
+
\ No newline at end of file
diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/sim/varcache/Topic_open_loop_2students/checksumOfCache.mat b/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/sim/varcache/Topic_open_loop_2students/checksumOfCache.mat
new file mode 100644
index 0000000..faab583
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diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/sim/varcache/Topic_open_loop_2students/tmwinternal/simulink_cache.xml b/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/sim/varcache/Topic_open_loop_2students/tmwinternal/simulink_cache.xml
new file mode 100644
index 0000000..05b51cf
--- /dev/null
+++ b/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/sim/varcache/Topic_open_loop_2students/tmwinternal/simulink_cache.xml
@@ -0,0 +1,6 @@
+
+
+
+ FsNdBVIwoIz8t9SYuH3U8w==
+
+
\ No newline at end of file
diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/sim/varcache/Topic_open_loop_2students/varInfo.mat b/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/sim/varcache/Topic_open_loop_2students/varInfo.mat
new file mode 100644
index 0000000..41a11a4
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diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/sl_proj.tmw b/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/sl_proj.tmw
new file mode 100644
index 0000000..f768596
--- /dev/null
+++ b/6th-Semester-Spring-2024/SysCon/Final Project/Code for Students-1/Code for Students/slprj/sl_proj.tmw
@@ -0,0 +1,2 @@
+Simulink Coder project marker file. Please don't change it.
+slprjVersion: 10.0_078
\ No newline at end of file
diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/Draft1.log b/6th-Semester-Spring-2024/SysCon/Final Project/Draft1.log
new file mode 100644
index 0000000..bdc9c46
--- /dev/null
+++ b/6th-Semester-Spring-2024/SysCon/Final Project/Draft1.log
@@ -0,0 +1,24 @@
+Circuit: * C:\users\sharpe\Documents\Rowan\Rowan-Classes\6th-Semester-Spring-2024\SysCon\Final Project\Draft1.asc
+
+Limiting rise time of source v2 to 1.6e-07
+Limiting fall time of source v2 to 1.6e-07
+Direct Newton iteration for .op point succeeded.
+
+Date: Tue Apr 16 21:35:31 2024
+Total elapsed time: 843.348 seconds.
+
+tnom = 27
+temp = 27
+method = modified trap
+totiter = 114326713
+traniter = 114326705
+tranpoints = 33186575
+accept = 24915937
+rejected = 8270638
+matrix size = 6
+fillins = 0
+solver = Normal
+Avg thread counts: 1.0/1.0/1.0/1.0
+Matrix Compiler1: 146 bytes object code size 0.3/0.2/[0.2]
+Matrix Compiler2: 366 bytes object code size 0.2/0.3/[0.2]
+
diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/Draft1.net b/6th-Semester-Spring-2024/SysCon/Final Project/Draft1.net
new file mode 100644
index 0000000..56540b6
--- /dev/null
+++ b/6th-Semester-Spring-2024/SysCon/Final Project/Draft1.net
@@ -0,0 +1,14 @@
+* C:\users\sharpe\Documents\Rowan\Rowan-Classes\6th-Semester-Spring-2024\SysCon\Final Project\Draft1.asc
+V1 N002 0 500
+R1 N004 0 1000
+L1 N003 N004 500µ
+C1 N004 0 470µ
+D1 0 N003 D
+S1 N003 N002 N001 0 Switch1
+V2 N001 0 PULSE(0 5 0 0 0 2.4u 4u)
+.model D D
+.lib C:\users\sharpe\AppData\Local\LTspice\lib\cmp\standard.dio
+.tran 1
+.model Switch1 SW(Ron=1 Roff=1Meg Vt=0.5 Vh=-0.4)
+.backanno
+.end
diff --git a/6th-Semester-Spring-2024/SysCon/Final Project/Draft1.op.raw b/6th-Semester-Spring-2024/SysCon/Final Project/Draft1.op.raw
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