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Finished DSP lab 4

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This commit is contained in:
Aidan Sharpe
2024-04-17 22:51:14 -04:00
parent df7d52f4b1
commit 98168e00bd
9 changed files with 155 additions and 114 deletions
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14
6th-Semester-Spring-2024/SysCon/Final Project/Draft1.net
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* C:\users\sharpe\Documents\Rowan\Rowan-Classes\6th-Semester-Spring-2024\SysCon\Final Project\Draft1.asc
V1 N002 0 500
R1 N004 0 1000
L1 N003 N004 500<30>
C1 N004 0 470<37>
D1 0 N003 D
S1 N003 N002 N001 0 Switch1
V2 N001 0 PULSE(0 5 0 0 0 2.4u 4u)
.model D D
.lib C:\users\sharpe\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1
.model Switch1 SW(Ron=1 Roff=1Meg Vt=0.5 Vh=-0.4)
.backanno
.end